MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 332

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Audio Interface Module (AIM)
1
17.7.7
17.7.7.1
The audio tick interrupt is an interrupt to sustain an interrupt routine that is synchronous with one of the
audio interfaces, but not directly related to any FIFO being full or empty. Two fields control how this
interrupt is generated:
For example, if the source is set to IIS1 Tx FIFO / Read, and count is set to three, the interrupt will occur
after every three read strobes to the IIS1 Tx FIFO. Even if the FIFO is in reset state, the interrupt will
continue running.
17.7.7.2
With FIFO’s feeding data to the PDIR registers, three interrupts are associated.
17-34
11, 2–0 AUDIO TICK SOURCE
Field
5–3
6
1. The source field controls the source event.
2. The count field controls the number of events (sample pairs) between any two audioTick interrupts.
1. Full
2. Under/over
3. Resync
The automatic FIFO resynchronization can be switched on, and will avoid all mismatch between left and right
the software obeys following rules:
1.When left data is read or written to the left FIFO, in the same place of the program, data must be read or written to the
2.Writing or reading data to the FIFO ‘s must be at least 2 samples at the time. If there is a mis-match between Left-Right,
right
then this is approximately 10 micro-seconds. For 88 kHz, then this approximately 5 micro-seconds.)
the resync logic may go on only 1 sample clock after last data is read/written to the FIFO. Also acceptable is polling the
FIFO
PDIR1 FIFO AUTO SYNC
AUDIO TICK COUNT
FIFO
, if at least part of the time, 2 samples will be read/written to it.
Audio Interrupts
AudioTick Interrupts
PDIR1, PDIR2, and PDIR3, Interrupts
. Maximum time difference between left and right is 1/2 sample clock. (E.g. if the sample frequency is 44 kHz,
Table 17-19. audioGlob Register Field (0xCE) Descriptions (continued)
Name
MCF5253 Reference Manual, Rev. 1
0 Auto synchronization off
1 Auto synchronization on
000 1 Interrupt for every event
001 2 Interrupt for every 2 events
010 3
011 4
100 5
Other Reserved, unused
0 000 Off
0 001 IIS1 Tx Right FIFO / Read
0 010 IIS2 Tx Right FIFO / Read
0 011 EBU Tx Right FIFO / Read
0 100 IIS1 Rcv Data
0 101 IIS3 Rcv Data
0 110 Reserved
0 111 EBU1 Rcv Data
1 000 EBU2 Rcv Data
Description
1
Reset
Freescale Semiconductor
000
000
0
Notes
FIFO
‘s, if