MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 460

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Advanced Technology Attachment Controller (ATA)
23.6.4
Apart from PIO mode, the ATA interface supports also MDMA and UDMA mode to transfer data. DMA
mode can be used to receive data from the drive (DMA in transfer). In DMA receive mode, the protocol
engine will transfer data from the drive to the FIFO using multiword DMA or ultra DMA protocol. The
transfer will pause when one of following occurs:
When the cause of the transfer pausing is removed, the transfer restarts. The end of the transfer is signalled
by the drive to the host by asserting the ATA_INTRQ signal. Alternatively, the host can read the device
status register. In this register, the drive will also indicate if the transfer has ended.
The transfer of data from the FIFO into the memory is handled by the host system DMA. Whenever the
FIFO filling is above the alarm threshold, the DMA should read one packet of data from the FIFO, and
store this in main memory. In doing so, the DMA prevents the FIFO from getting full, and keeps the
transfer from drive to FIFO running.
The steps for setting up a DMA data transfer from device to host are:
23-34
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1. Make sure the ATA bus is not in reset and all timing registers are programmed.
2. Make sure the FIFO is empty by reading it until empty or by resetting it.
3. Initialize the DMA channel connected to fifo_rcv_alarm. Every time fifo_rcv_alarm is high, the
4. Write 2 * <packetsize> to fifo_alarm register. In this way, FIFO will request attention to DMA
5. To make the ATA ready for a DMA transfer from device to host, take the following steps:
6. Now, the host side of the DMA is ready. Send commands to the drive in PIO mode that cause it to
7. When the drive now requests DMA transfer by pulling ATA_DMARQ high, the ATA interface will
8. During the transfer, the host can monitor for end of transfer by reading some device ATA registers.
9. On end of transfer, the host or host DMA should wait until controller_idle is set, and next read the
The FIFO is full.
The drive deasserts its dma request signal ATA_DMARQ.
The bit dma_pending in the ata_contol register is cleared.
DMA should read <packetsize> long ints from the FIFO, and store them to main memory. (typical
packetsize is 8 longs)
when there is at least one packet ready for transfer.
a) Make sure the FIFO is out of reset by setting bit fifo_rst_b to 1 in the ata control register.
b) Program fifo_rcv_en=1 in decontrol register. This enables the FIFO to by emptied by the DMA.
c) Program dma_pending =1, dma_write=0, ultra_mode_selected=0/1 in ata_control register.
request DMA transfer on the ATA bus. The nature of these commands is beyond the scope of this
document. You should consult the ATA specification to know how to communicate with the drive.
acknowledge with ATA_DMACK, and the transfer will start. Data is transferred automatically to
the FIFO, and from there on to the host memory.
These reads will cause the running DMA to pause; after the read is completed, the DMA resumes.
The host can also wait unit the drive asserts ATA_INTRQ. This also indicates end of transfer.
remaining halfwords from the FIFO, and transfer these to memory.
ultra_mode_selected should be 1 if you want to transfer data using UDMA mode, it should be
0 if you want to transfer data using MDMA mode.
Using DMA Mode to Receive Data from ATA Bus
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor