SI1011-A-GM Silicon Laboratories Inc, SI1011-A-GM Datasheet - Page 226

• Manufacturer Part Number: SI1011-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1011-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1872-5

Si1010/1/2/3/4/5
SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0
SFR Page = 0x0; SFR Address = 0xE1
226
Note: SPI0 can be assigned either 3 or 4 Port I/O pins.
Name
Reset
Type
Bit
Bit
7
6
5
4
3
2
1
0
SYSCKE SYSCLK Output Enable.
CP1AE
CP1AE
CP0AE
SMB0E
URT0E
SPI0E
Name
CP1E
CP0E
R/W
7
0
Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 output unavailable at Port pin.
1: Asynchronous CP1 output routed to Port pin.
Comparator1 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 output unavailable at Port pin.
1: Asynchronous CP0 output routed to Port pin.
Comparator0 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
0: SYSCLK output unavailable at Port pin.
1: SYSCLK output routed to Port pin.
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pin.
1: SDA and SCL routed to Port pins.
SPI0 I/O Enable.
0: SPI0 I/O unavailable at Port pin.
1: SCK, MISO, and MOSI (for SPI0) routed to Port pins.
UART0 Output Enable.
0: UART I/O unavailable at Port pin.
1: TX0 and RX0 routed to Port pins P0.4 and P0.5.
CP1E
NSS (for SPI0) routed to Port pin only if SPI0 is configured to 4-wire mode.
R/W
6
0
CP0AE
R/W
5
0
CP0E
R/W
Rev. 1.0
4
0
Function
SYSCKE
R/W
3
0
SMB0E
R/W
2
0
SPI0E
R/W
1
0
URT0E
R/W
0
0