SI1011-A-GM Silicon Laboratories Inc, SI1011-A-GM Datasheet - Page 245

• Manufacturer Part Number: SI1011-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1011-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1872-5

SFR Definition 22.2. SPI1CN: SPI Control
SFR Page = 0x0; SFR Address = 0xB0; Bit-Addressable
Name
Reset
Bit
3:2
Type
7
6
5
4
1
0
Bit
NSS1MD[1:0] Slave Select Mode.
TXBMT1
WCOL1
MODF1
SPI1EN
SPIF1
SPIF1
Name
R/W
7
0
WCOL1 MODF1
R/W
6
0
SPI1 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are
enabled, setting this bit causes the CPU to vector to the SPI1 interrupt service
routine. This bit is not automatically cleared by hardware. It must be cleared by
software.
Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI1 interrupt) to indicate a
write to the SPI1 data register was attempted while a data transfer was in progress.
It must be cleared by software.
Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI1 interrupt) when a mas-
ter mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01).
This bit is not automatically cleared by hardware. It must be cleared by software.
Reserved.
Read = varies; Write = must write zero.
Must be set to 00b. SPI1 can only be used in 3-wire master mode.
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
SPI1 Enable.
0: SPI1 disabled.
1: SPI1 enabled.
R/W
5
0
R/W
4
0
Rev. 1.0
NSS1MD1
R/W
3
0
Function
NSS1MD0
R/W
2
1
Si1010/1/2/3/4/5
TXBMT1
R
1
1
SPI1EN
R/W
0
0
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