SI1011-A-GM Silicon Laboratories Inc, SI1011-A-GM Datasheet - Page 244

• Manufacturer Part Number: SI1011-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1011-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1872-5

Si1010/1/2/3/4/5
22.6. SPI Special Function Registers
SPI1 is accessed and controlled through four special function registers in the system controller: SPI1CN
Control Register, SPI1DAT Data Register, SPI1CFG Configuration Register, and SPI1CKR Clock Rate
Register. The special function registers related to the operation of the SPI1 Bus are described in the follow-
ing figures.
SFR Definition 22.1. SPI1CFG: SPI Configuration
SFR Page = 0x0; SFR Address = 0x84
244
*Note: In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum
Name
Reset
Bit
3:0
Type
7
6
5
4
Bit
settling time for the slave device. See Table 22.2 for timing parameters.
Reserved
SPIBSY
MSTEN
CKPHA
CKPOL
SPIBSY
Name
R
7
0
MSTEN
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress.
Master Mode Enable.
When set to 1, enables master mode. This bit must be set to 1 to communicate
with the EZRadioPRO peripheral.
SPI Clock Phase.
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
SPI Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Read = 0000, Write = don’t care.
R/W
6
0
CKPHA
R/W
5
0
CKPOL
R/W
Rev. 1.0
4
0
Function
R
3
0
*
*
R
2
1
R
1
1
R
0
1