SI1011-A-GM Silicon Laboratories Inc, SI1011-A-GM Datasheet - Page 268

• Manufacturer Part Number: SI1011-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1011-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1872-5

Si1010/1/2/3/4/5
23.5.6. Synthesizer
An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is
provided on-chip. Using a ΣΔ synthesizer has many advantages; it provides flexibility in choosing data
rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the
loop in the digital domain through the fractional divider which results in very precise accuracy and control
over the transmit deviation.
Depending on the part, the PLL and  -  modulator scheme is designed to support any desired frequency
and channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band)
or 312.5 Hz (High band). The transmit data rate can be programmed between 0.123–256 kbps, and the
frequency deviation can be programmed between ±1–320 kHz. These parameters may be adjusted via
registers as shown in “Frequency Control” on page 255.
TX
Selectable
Fref = 10 M
PFD
CP
LPF
RX
Divider
VCO
N
Delta-
TX
Modulation
Sigma
Figure 23.10. PLL Synthesizer Block Diagram
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-
chip inductors. The output of the VCO is followed by a configurable divider which will divide down the sig-
nal to the desired output frequency band. The modulus of the variable divide-by-N divider stage is con-
trolled dynamically by the output from the  -  modulator. The tuning resolution is sufficient to tune to the
commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240–
960 MHz.
23.5.6.1. VCO
The output of the VCO is automatically divided down to the correct output frequency depending on the
hbsel and fb[4:0] fields in "Register 75h. Frequency Band Select". In receive mode, the LO frequency is
automatically shifted downwards by the IF frequency of 937.5 kHz, allowing transmit and receive operation
on the same frequency. The VCO integrates the resonator inductor and tuning varactor, so no external
VCO components are required.
The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will
automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this
might not be desirable so the VCO calibration may be skipped by setting the appropriate register.
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Rev. 1.0