SI1011-A-GM Silicon Laboratories Inc, SI1011-A-GM Datasheet - Page 367

• Manufacturer Part Number: SI1011-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1011-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1872-5

Where F
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn
register. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the
CCFn flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare
register for the channel are equal.
28.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width modulated (PWM) output on its
associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer,
and the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit
PWM mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-
bit PWM modes. It is important to note that all channels configured for 8/9/10/11-bit PWM mode will
use the same cycle length. It is not possible to configure one channel for 8-bit PWM mode and another
for 11-bit mode (for example). However, other PCA channels can be configured to Pin Capture, High-
Speed Output, Software Timer, Frequency Output, or 16-bit PWM mode independently.
28.3.5.1.
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn
capture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 28.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 28.2.
Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0
Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
PCA0CPLn
Write to
Reset
PCA0CPHn
PCA
Write to
8-Bit Pulse Width Modulator Mode
is the frequency of the clock selected by the CPS2 – 0 bits in the PCA mode register,
0
ENB
ENB
1
W
M
P
1
6
n
x
C
O
M
E
n
Figure 28.7. PCA Frequency Output Mode
PCA0CPMn
C
A
P
P
n
0 0 0
C
A
P
N
n
Equation 28.2. 8-Bit PWM Duty Cycle
M
A
T
n
Duty Cycle
T
O
G
n
W
P
M
n
C
C
E
F
n
x
PCA Timebase
Enable
=
Rev. 1.0
Comparator
PCA0CPLn

-------------------------------------------------- -
256 PCA0CPHn
PCA0L
8-bit
–
256
match
Enable
Adder
8-bit Adder
Toggle

Si1010/1/2/3/4/5
TOGn
0
1
CEXn
PCA0CPHn
Crossbar
Port I/O
367