SI1011-A-GM Silicon Laboratories Inc, SI1011-A-GM Datasheet - Page 272

• Manufacturer Part Number: SI1011-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1011-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1872-5

Add R/W
Add R/W
7C
7D
08
7E
Si1010/1/2/3/4/5
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When
the incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcon-
troller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.
Both the TX and RX FIFOs may be cleared or reset with the ffclrtx and ffclrrx bits. All interrupts may be
enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and “Register 06h. Inter-
rupt Enable 2.” If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin
but the bits will still be read correctly in the Interrupt Status registers.
23.6.2. Packet Configuration
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. "Reg-
ister 30h. Data Access Control" through “Register 4Bh. Received Packet Length” control the configuration,
status, and decoded RX packet data for Packet Handling. The usual fields for network communication
(such as preamble, synchronization word, headers, packet length, and CRC) can be configured to be auto-
matically added to the data payload. The fields needed for packet generation normally change infrequently
and can therefore be stored in registers. Automatically adding these fields to the data payload greatly
reduces the amount of communication between the microcontroller and the transceiver.
The general packet structure is shown in Figure 23.12. The length of each field is shown below the field.
The preamble pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields
have programmable lengths to accommodate different applications. The most common CRC polynominals
are available for selection.
An overview of the packet handler configuration registers is shown in Table 23.4.
272
R/W
R/W
R/W
R/W
1-255 Bytes
Preamble
Description
Description
Operating &
Function/
Function/
Control 2
Control 1
Control 2
Function
TX FIFO
TX FIFO
RX FIFO
Control
1-4 Bytes
Reserved Reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0]
Reserved Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h
Reserved Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0]
antdiv[2]
D7
D7
Figure 23.12. Packet Structure
antdiv[1]
D6
D6
antdiv[0]
D5
D5
Rev. 1.0
rxmpk
D4
D4
Data
autotx
D3
D3
enldm
D2
D2
ffclrrx
D1
D1
0 or 2
Bytes
CRC
ffclrtx
D0
D0
POR
Def.
37h
POR
Def.
00h
37h