WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet
WJLXT385LE.B1
Specifications of WJLXT385LE.B1
Related parts for WJLXT385LE.B1
WJLXT385LE.B1 Summary of contents
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Intel LXT385 Octal E1 Short-Haul PCM Transceiver with Jitter Attenuation (JA) Product Features OctalE1 Pulse-Code Modulation (PCM) Transceiver with Jitter Attenuation for use in 2.048 Mbps (E1) applications 8 fully-independent receiver/transmitters Support for E1 standards: — Exceeds ETSI ETS ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE ...
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... Microprocessor-Standard Bus and Interface Signals .......................................... 30 5.3 Framer/Mapper Signals....................................................................................... 33 5.3.1 Bipolar vs. Unipolar Operation - Receive Side ....................................... 33 5.3.2 Bipolar vs. Unipolar Operation - Transmit Side ...................................... 34 5.3.3 Framer/Mapper Signals - Details............................................................ 35 5.4 Line Interface Unit Signals .................................................................................. 40 5.5 Clocks and Clock-Related Signals ...................................................................... 43 5.6 Configuration and Mode-Select Signals .............................................................. 45 5.7 Signal Loss and Line-Code-Violation Signals ..................................................... 47 5 ...
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Contents 6.7 Loopbacks ........................................................................................................... 67 6.7.1 Analog Loopback ................................................................................... 67 6.7.2 Digital Loopback..................................................................................... 68 6.7.3 Remote Loopback .................................................................................. 69 6.8 Transmit All Ones Operations ............................................................................. 70 6.8.1 TAOS Generation................................................................................... 70 6.8.2 TAOS Generation with Analog Loopback .............................................. 71 6.8.3 TAOS ...
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... Receiver Bipolar/Unipolar I/O Signal Functions .................................................. 27 6 Transmitter Bipolar/Unipolar I/O Signal Functions .............................................. 28 7 Microprocessor-Standard Bus and Interface Signals .......................................... 30 8 Framer/Mapper Receive Signals .........................................................................35 9 Framer/Mapper Transmit Signals........................................................................ 37 10 Line Interface Unit Signals .................................................................................. 40 11 Clocks and Clock-Related Signals ...................................................................... 43 12 Configuration and Mode-Select Signals .............................................................. 45 13 Signal Loss and Line-Code-Violation Signals ...
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... Operating Mode-Specific Signal Names ............................................................. 26 5 Receiver Bipolar/Unipolar I/O Signal Functions .................................................. 27 6 Transmitter Bipolar/Unipolar I/O Signal Functions .............................................. 28 7 Microprocessor-Standard Bus and Interface Signals .......................................... 30 8 Framer/Mapper Receive Signals......................................................................... 35 9 Framer/Mapper Transmit Signals........................................................................ 37 6 ® LXT385 Transceiver ...... 89 Datasheet Document Number: 249252 Revision Number: 006 Revision Date: 19-Jan-2006 ...
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Line Interface Unit Signals .................................................................................. 40 11 Clocks and Clock-Related Signals ...................................................................... 43 12 Configuration and Mode-Select Signals .............................................................. 45 13 Signal Loss and Line-Code-Violation Signals ..................................................... 47 14 Performance-Monitoring Selections with A3:0 Pins ............................................ 48 15 Power and ...
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Contents ® 59 Intel LXT385 Transceiver AC Receiver Characteristics .................................. 107 ® 60 Intel LXT385 Transceiver Transmit Timing Characteristics............................. 109 ® 61 Intel LXT385 Transceiver Receive Timing Characteristics ............................. 110 ® 62 Intel Processor - Read Timing Characteristics................................................ 111 ® ...
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Revision History Page Number 135 Added 135 Added 136 Added LXT385 product and revision numbers, etc. to 137 Added Page Number 17 Changed text in Page Number Major editing/rewriting/reorganizing, based on results of extensive testing of this device, and on ...
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... Section 3.2.1, “Loss of Signal Detector”. Text changed. 27 Section 3.2.1.1, “G.755 and ETSI 300 233 - Loss of Signal Detection”. Text changed. 28 New Section 5.3, “Framer/Mapper Signals”, added from old Chapter 2. Table text changed. 29 Section 3.3, “Transmitter”. Text changed. 30 Section 3.4, “Transmitter Output Driver Power and Grounds”. Text changed. ...
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Information from old Section 3.2.1, “Loss of Signal Detector”, re-numbered to new Section 6.3.3, 50 “Receiver Loss-Of-Signal Detector”, and text changed. Information from old Section 3.2.1, “Loss of Signal Detector”, re-numbered to new Section 6.3.3, 50 “Receiver Loss-Of-Signal Detector”, and ...
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Contents Information from old Section 3.6.4, “Transmit All Ones (TAOS)”, moved to new Section 6.8.3, 70 “TAOS Generation with Digital Loopback”, and added new Figure 22 “TAOS Generation with Digital Loopback for Intel Old Section 4.4, “Serial Host Mode”, changed ...
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Old Table 19, “Global Control Register, GCR (0Fh)”, changed to new Table 37, “Global Control 80 Register, GCR - 0Fh” and table text changed. Old Figure 5, “AMI 50% AMI Encoding”, moved to new Table 37. Old Table 23, “AIS ...
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Contents Page Number 26 Section 3.2, “Receiver”. Text changed. 27 Old section 3.2.1.1, “E1 Mode” title changed to new Section 3.2.1.1,”G.755 and ETSI 300 233 - Loss of Signal Detector”. - Old section 3.2.2.1, “E1 Mode” title was deleted. 28 ...
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Page Number 10 Old Figure 1, “LXT Block Diagram”, changed to new Figure 1, “Intel® LXT385 Transceiver High-Level Block Diagram”. 25 Section 3.1, “Initialization”. Text changed. 26 Section 3.2, “Receiver”. Text changed. 27 Old section 3.2.1.1, “E1 Mode” title changed ...
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Contents Page Number - Initial release. 16 ® Intel LXT385 Transceiver - Revision 001 Revision Date: January 2001 Description Datasheet Document Number: 249252 Revision Number: 006 Revision Date: 19-Jan-2006 ...
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Introduction to this Document 1.1 Audience and Purpose The audience for this document is design engineers. The purpose of this document is to provide design information about the Intel Short-Haul Pulse-Code Modulation Transceiver with Jitter Attenuation (called hereafter the ...
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... LXD384 - Evaluation Board for Octal T1/E1 Applications - Developer Manual ® Intel LXT380/1/4/6/8 Redundancy Applications - Application Note ® Intel LXT380/4 Octal T1/E1 LIUs - Interfacing with the Transwitch Octal Framers - Application Note ® Intel LXT384 Octal LIU and Intel Power-Up Rise Time - Application Note ® ...
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Product Summary The LXT385 Transceiver is designed for use in 2.048-Mbps applications. It incorporates eight independent receivers and eight independent transmitters in either a single 144-pin LQFP or a 160- ball PBGA package. Transmitters. The LXT385 transceiver transmits shaped ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Figure high-level block diagram of the LXT385ransceiver. ® Figure 1. Intel LXT385 Transceiver High-Level Block Diagram JTAG Serial/ Parallel Port RTIP RRING TTIP TRING JA = Jitter ...
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Figure detailed block diagram of the LXT385ransceiver. ® Figure 2. Intel LXT385 Transceiver Detailed Block Diagram JTAG SERIAL/ PARALLEL PORT Transceiver 7 RTIP7 RRING7 TTIP7 TRING7 RTIP6/RRING6 TTIP6/TRING6 RTIP5/RRING5 TTIP5/TRING5 Transceiver 4 RTIP4/RRING4 TTIP4/TRING4 RTIP3/RRING3 TTIP3/TRING3 RTIP2/RRING2 ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 3.0 Pin Assignments and Package Table 2 lists the top-side markings for the LXT385ransceiver, which has two packages: • A 144-pin Low-Profile Octal-Flat Package, or ‘LQFP’ • A 160-ball Plastic ...
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Figure 3 shows a top view of the LXT385ransceiver Low-profile Octal Flat Pack (LQFP) package, with pin assignments. For package information, see ® Figure 3. Intel LXT385 Transceiver LQFP Package - 144-Pin Assignments TPOS7/TDATA7 1 TCLK7 2 LOS6 3 RNEG6/BPV6 ...
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... TGND TTIP RRING RRING TRING TGND RTIP RTIP TGND TRING TTIP TGND TGND TTIP RRING RRING LIU Intel® LXT385 Framer (BOTTOM VIEW) TTIP TGND TGND TTIP RRING RRING TRING TGND RTIP RTIP TGND TRING TTIP TGND TGND TTIP RRING RRING 3 3 ...
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Multi-Function Pins The LXT385 ransceiver has several pins that have more than one name and more than one function, depending on the mode selected. This chapter lists the multi-function pins. Descriptions of signal functions are in 4.1 Operating Mode ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 4. Operating Mode-Specific Signal Names 1. Hardware Mode QFP PBGA Pin Ball Signal Signal Name Function Must connect to ground Use for perfor- ...
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... Framer/Mapper I/O Pins Depending on the state of a UBS7:0 pin, both the corresponding receiver and transmitter pins are automatically set for either bipolar I/O or unipolar I/O. When a UBS pin is connected: • Low, bipolar I/O is selected. • High for more than 16 consecutive MCLK clock cycles, unipolar I/O is selected. ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 6 lists LXT385 ransceiver transmitter pins that have different names and functions depending on the I/O mode selected. Table 6. Transmitter Bipolar/Unipolar I/O Signal Functions Pins Balls Bipolar I/O ...
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... Signal Groupings Signal groupings discussed in this chapter include the following: • Section 5.2, “Microprocessor-Standard Bus and Interface Signals” • Section 5.3, “Framer/Mapper Signals” • Section 5.4, “Line Interface Unit Signals” • Section 5.5, “Clocks and Clock-Related Signals” ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 5.2 Microprocessor-Standard Bus and Interface Signals Table 7 lists and describes the microprocessor-standard bus and interface signals for the LXT385 ransceiver. For multi-function pins, the pin name in Note: For ...
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Table 7. Microprocessor-Standard Bus and Interface Signals (Sheet Signal QFP Name Pin CS / JASEL LOOP7 LOOP6 LOOP5 LOOP4 LOOP3 24 D2 ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 7. Microprocessor-Standard Bus and Interface Signals (Sheet Signal QFP Name Pin ACK / RDY / 83 SDO RD / R/W 85 ALE / ...
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... In this case, the signal flow occurs as follows: 1. RDATA and RCLK connect the LXT385 ransceiver to a framer/mapper, while BPV acts as a bipolar violation detector. The LXT385 ransceiver internally decodes HDB3/AMI. 2. The receiver outputs the recovered clock at RCLK. RCLK synchronizes the data transfer into the framer/mapper ...
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... Intel LXT385 Octal E1 S/H PCM Transceiver with JA 5.3.2 Bipolar vs. Unipolar Operation - Transmit Side Table 6 on page 28 lists transmit-side framer/mapper signals, which connect to a framer/mapper using either bipolar or unipolar interface connections. • TDATA - works in combination with BPV outputs, in unipolar mode. • TNEG - works in combination with TPOS, in bipolar mode. ...
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... AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. Document Number: 249252 Revision Number: 006 Revision Date: 19-Jan-2006 ® Intel LXT385 Octal E1 S/H PCM Transceiver with JA lists and describes the LXT385 ransceiver framer/mapper transmit signals. blue bold print indicates the signal being discussed. QFP PBGA Signal Pin ...
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... Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 8. Framer/Mapper Receive Signals (Sheet Signal QFP Name BPV7 / RNEG7 BPV6 / RNEG6 BPV5 / RNEG5 BPV4 / RNEG4 BPV3 / RNEG3 BPV2 / RNEG2 BPV1 / RNEG1 BPV0 / RNEG0 RDATA7 / RPOS7 RDATA6 / RPOS6 RDATA5 / RPOS5 RDATA4 / RPOS4 RDATA3 / ...
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... Table 9. Framer/Mapper Transmit Signals (Sheet Signal Name TCLK7 TCLK6 TCLK5 TCLK4 TCLK3 TCLK2 TCLK1 TCLK0 Document Number: 249252 Revision Number: 006 Revision Date: 19-Jan-2006 ® Intel LXT385 Octal E1 S/H PCM Transceiver with JA QFP PBGA Signal Pin Ball Type Transmit Clock Input 7:0. ...
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... Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 9. Framer/Mapper Transmit Signals (Sheet Signal QFP Name TNEG7 / UBS7 TNEG6 / UBS6 TNEG5 / UBS5 TNEG4 / UBS4 TNEG3 / UBS3 TNEG2 / UBS2 TNEG1 / UBS1 TNEG0 / UBS0 TNEG7 / UBS7 TNEG6 / UBS6 TNEG5 / UBS5 TNEG4 / UBS4 TNEG3 / ...
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... Table 9. Framer/Mapper Transmit Signals (Sheet Signal Name TDATA7 / TPOS7 TDATA6 / TPOS6 TDATA5 / TPOS5 TDATA4 / TPOS4 TDATA3 / TPOS3 TDATA2 / TPOS2 TDATA1 / TPOS1 TDATA0 / TPOS0 Document Number: 249252 Revision Number: 006 Revision Date: 19-Jan-2006 ® Intel LXT385 Octal E1 S/H PCM Transceiver with JA QFP ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 5.4 Line Interface Unit Signals For multi-function pins, the pin name in Table 10. Line Interface Unit Signals (Sheet Signal QFP Name Pin D7 / LOOP7 28 ...
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Table 10. Line Interface Unit Signals (Sheet Signal QFP Name Pin OE 114 RRING7 138 RRING6 133 RRING5 126 RRING4 121 RRING3 66 RRING2 61 RRING1 54 RRING0 49 RTIP7 139 RTIP6 132 RTIP5 127 RTIP4 120 ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 10. Line Interface Unit Signals (Sheet Signal QFP Name Pin TTIP7 136 TTIP6 129 TTIP5 124 TTIP4 117 TTIP3 64 TTIP2 58 TTIP1 52 TTIP0 45 ...
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Clocks and Clock-Related Signals Table 11 lists and describes LXT385 ransceiver clocks and clock-related signals. Note: Within this table, ‘RCLK’ references RCLK7:0 and ‘TCLK’ references TCLK7:0. Each RCLK and TCLK signal is used with corresponding signals. • Example: RCLK6 ...
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... For information on SCLK, see Bus and Interface Signals”. Transmit Clock Input 7:0. For information on TCLK, see Signal Description Section Protection”. Section 5.3, “Framer/Mapper Signals”. Section 5.2, “Microprocessor-Standard Section 5.3, “Framer/Mapper Signals”. Document Number: 249252 Revision Number: 006 Revision Date: 19-Jan-2006 ...
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Configuration and Mode-Select Signals Table 12 lists and describes the LXT385 ransceiver configuration and mode-select signals. For multi-function pins, the pin name in Table 12. Configuration and Mode-Select Signals (Sheet Signal QFP Name Pin CODEN / ...
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... Parallel Interface Timing” Unipolar/Bipolar Select Input 7:0. D3 For information on the UBS signals, see Mapper Signals”. D12 B12 N12 L12 L3 N3 and Ground. CC Section 11.2, “Host Processor Mode - Section 5.3, “Framer/ Document Number: 249252 Revision Number: 006 Revision Date: 19-Jan-2006 ...
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... Section 6.3.3, “Receiver Loss-Of-Signal Receive Clock Output 7:0. For information on how RCLK is used for clock and data recovery, see Section 5.3, “Framer/Mapper Signal Description Table 14. A4 must be connected Section 5.2, “Microprocessor- Signals”). Section 5.3, “Framer/ Signals”. Detector”.) Signals”. 47 ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 14 lists performance-monitoring selections that can be made when the LXT385 ransceiver is in the Hardware mode. Table 14. Performance-Monitoring Selections with A3:0 Pins Signal QFP PBGA Name Pin ...
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Power and Grounds Table 15 lists and describes the LXT385 ransceiver power and grounds. For low-noise operation, the LXT385 ransceiver is designed so that each transmitter has its own power and its own ground. These pins are not necessarily ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 5.9 Test Signals Table 17 lists and describes the LXT385 ransceiver test signals, which are used to test all digital input, output, and input/output pins. The JTAG test signals are ...
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Functional Description This functional description chapter follows the flow of signals through an LXT385 ransceiver. This chapter discusses the following topics: • Section 6.1, “Functional Overview” • Section 6.2, “Initialization and Reset” • Section 6.3, “Receiver” • Section 6.4, ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 6.1 Functional Overview The LXT385 ransceiver is a fully integrated octalline interface unit designed for 2.048 Mbps short-haul applications. (For a block diagram, see The LXT385 ransceiver can be controlled ...
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Receiver The LXT385 ransceiver has eight identical receivers. 6.3.1 Receiver Clocking In the receive mode, clocking for the LXT385 ransceiver receiver depends on the following. When the LXT385 ransceiver is in: • Clock-recovery mode, the RCLK pin provides the ...
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... Jitter Tolerance Compared to ITU G.823” on page 128 — Depending on the options selected, recovered clock and data signals may be routed through the jitter attenuator, through the HDB3/AMI decoder, and may be output to the framer as either bipolar or unipolar data. 6.3.3 Receiver Loss-Of-Signal Detector The LXT385 ransceiver loss-of-signal (LOS) detector circuit is designed to detect loss of signals in both analog and digital domains ...
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Receiver Data Recovery Mode In data-recovery mode, the combined analog/digital LOS detector circuit uses only its LOS analog part, which complies with the ITU-G.775 recommendation. The LOS digital timing is derived from an internal self-timed circuit. RPOS/RNEG stay active ...
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... Next, the RDATA pin acts as the receive data output. (For details on the BPV and RDATA pin functions, see 56 89) Section 6.3.3, “Receiver Loss-Of-Signal Section 5.3, “Framer/Mapper Signals”.) Table 45, “AIS Interrupt Enable Detector”) detects an in- Document Number: 249252 Revision Number: 006 ...
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Transmitter The LXT385 ransceiver has eight identical transmitters. 6.4.1 Transmitter Clocking The eight low-power transmitters of the LXT385 ransceiver are identical. Transmit data is clocked serially into the device at TPOS/TNEG in bipolar mode TDATA in unipolar ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA If TCLK: • Is not supplied, the transmitter output remains powered down and the TTIP/TRING outputs are held in a high-impedance tristate. Fast output tristatability is also available through the ...
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In the Hardware mode, if TCLK is connected high 16 consecutive MCLK clock cycles and MCLK is: • Not supplied (or ‘low’), the transmit pulse-shaper circuit shown in is, disabled). In this case, TPOS and TNEG control the pulse width ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 6.4.2.1 Output Driver Power Supply The output driver power supply (TVCC pins) can be either 3. nominal. • When TVCC=5V, theLXT385 ransceiver drives 75Ω/120Ω lines through a 1:2 ...
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Transmitter Output Driver Power and Grounds Each output driver is supplied by its own separate TVCC and TGND pins. The TVCC pins can be either 3 nominal. The LXT385 ransceiver drives either a 75Ω coaxial ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 6.5 Line-Interface Protection Figure 6 shows circuitry for line-interface protection. (While not mandatory for normal operation, ® Intel strongly recommends these line-interface protection elements.) For the appropriate values and tolerances ...
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Figure 6. Intel LXT385 Transceiver External Transmit/Receive Line Interface Circuitry TVCC 0.1μF 1 3.3V VCC 0.1μF GND Intel ® LXT385 Transceiver (ONE CHANNEL) 1 Common decoupling capacitor for all TVCC and TGND pins. 2 Typical value. Adjust for actual ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 18 lists the component values to use with power used and the type of cable with which the component is used. Table 18. Component Values to Use with Transformer ...
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Jitter Attenuation Figure 7 shows the internal LXT385 ransceiver jitter attenuation (JA) unit, which requires neither an external crystal nor a reference clock that has a frequency higher than the line frequency. Data signals are clocked into the FIFO ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA When the LXT385 ransceiver is in the: • Host Processor mode: — The Global Control Register (GCR, positioned in the receive or transmit path. — Depending on the GCR register ...
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Loopbacks For diagnostics, the LXT385 ransceiver has the following loopback modes: • Section 6.7.1, “Analog Loopback” • Section 6.7.2, “Digital Loopback” • Section 6.7.3, “Remote Loopback” To select a loopback mode when the mode is in: • Hardware mode, ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 6.7.2 Digital Loopback The digital loopback function is available in the Host Processor mode only. AsFigure 9 shows, when digital loopback is selected, the transmit clock TCLK and transmit data ...
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Remote Loopback AsFigure 10 shows, when a remote loopback is selected, the RCLK, RPOS, and RNEG outputs route to the transmit circuits, and data are output on the TTIP and TRING pins. (For the LOOP pin settings that select ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 6.8 Transmit All Ones Operations For Transmit All Ones (TAOS) operations, the LXT385 ransceiver has the following TAOS modes: • Section 6.8.1, “TAOS Generation” • Section 6.8.2, “TAOS Generation with ...
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TAOS Generation with Analog Loopback Figure 12 shows how the TAOS mode affects the receive path after analog loopback. Figure 12. TAOS Generation with Analog Loopback for Intel MCLK TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled 6.8.3 ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 6.9 Performance Monitoring The LXT385 ransceiver can be set for either one of the following configurations: • All eight channels 0 through 7 operating as regular transceivers • Channels 1 ...
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Intel Hitless Protection Switching The LXT385 ransceiver has a feature that allows used in an Intel Switching application. Intel method that uses very fast silicon switching instead of slow mechanical relays. This method is best ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 7.0 Operating Mode Summary This section discusses the following operating modes: • Section 7.1, “Interfacing with 5V Logic” • Section 7.2, “Hardware Mode” • Section 7.3, “Hardware Mode Settings” • ...
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Hardware Mode Settings Table 20 lists LXT385 ransceiver hardware mode settings for receive, transmit, and loopback operations. ® Table 20. Intel LXT385 Transceiver Hardware Mode Settings for Receive, Transmit, and Loopback MCLK TCLK (Table 11) (Table 8) Low Low ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 7.4 Host Processor Modes When the MODE pin is connected high, the following Host Processor modes are available. • Section 7.4.1, “Host Processor Mode - Parallel Interface” • Section 7.4.2, ...
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Host Processor Mode - Parallel Interface, Motorola* Processor The Motorola processor interface is selected by asserting the LXT385 ransceiver MOT/INTL pin low. The R/W signal indicates if a data transfer read or write. The DS ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 7.4.2 Host Processor Mode - Serial Interface A Host Processor mode with a serial interface consisting of the CS, SCLK, SDI, and SDO pins is selected by connecting the MODE ...
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Interrupt Handling 7.5.1 Interrupt Sources Interrupt sources include the following: 1. Status change in the LOS (Loss of Signal) Status register (04h, ransceiver continuously monitors the receiver signal and updates the specific LOS status bit to indicate either the ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 8.0 Registers This chapter discusses the LXT385 ransceiver registers. 8.1 Register Summary Table 22 lists LXT385 ransceiver registers by the hex address of each. ® Table 22. Intel LXT385 Transceiver ...
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Table 23 groups the LXT385 ransceiver registers by function and lists the bit names. Table 23. Register Bit Names Register Mne- Name monic ID, Reset, and Control Registers ID ID Reset RES Global Control GCR Loopback Registers Analog ALOOP Loopback ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 8.2 Register Addresses Table 24 lists the register names and register addresses on: • Pins A7:1 (used for the LXT385 ransceiver Host Processor mode with a serial interface) • Pins ...
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Register Descriptions Table 25. ID Register 00h Bit Name 7:0 ID7:0 Table 26. Analog Loopback Register, ALOOP - 01h Bit Name 7:0 AL7:0 Table 27. Remote Loopback Register, RLOOP - 02h Bit Name 7:0 RL7:0 Table 28. ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 29. LOS Status Monitor Register, LOS - 04h Bit Name Loss Of Signal Status Monitor. 7:0 LOS7:0 Table 30. DFM Status Monitor Register (05h) for Intel Bit Name 7:0 ...
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Table 35. Reset Register, RES - 0Ah Bit Name 7:0 RES7:0 Document Number: 249252 Revision Number: 006 Revision Date: 19-Jan-2006 ® Intel LXT385 Octal E1 S/H PCM Transceiver with JA Description Reset. The RES7:0 bits are used to set all ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 36 lists and describes the A3:0 bits that can be used to monitor the performance of one of either Receivers 1 through 7 or one of Transmitters 1 through ...
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Table 37. Digital Loopback Register 0Ch Bit Name 7:0 DL7:0 Table 38. LOS/AIS Criteria Selection Register, LACS - 0Dh Bit Name 7:0 LACS7:0 Table 39. Automatic TAOS Select Register, ATS - 0Eh Bit Name 7:0 ATS7:0 Document Number: ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 40. Global Control Register, GCR - 0Fh Bit Name 7 - Reserved. Receive Alarm Indication Signal Enable. This bit controls automatic AIS insertion in the receive path when LOS ...
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Table 41. Pulse Shaping Indirect Address Register, PSIAD (10h) 1 Bit Name 0-2 LENAD 0 power-on reset the register is set to “0”. Table 42. Pulse Shaping Data Register, PSDAT (11h) for Intel 1 ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 46. AIS Interrupt Status Register, AISIS - 15h Bit Name Alarm Indication Signal Interrupt Status. 7:0 AISIS7:0 90 Description • On power-up, all AISIS7:0 bits are cleared to ‘0’. ...
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JTAG Boundary Scan 9.1 Overview The LXT385 ransceiver supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition to the traditional IEE1149.1 digital boundary scan capabilities, theLXT385 ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 9.3 TAP Controller The TAP controller is a 16-state synchronous state machine controlled by the TMS input and clocked by TCK (see mode, receiving an instruction, receiving data, transmitting data ...
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Figure 16. JTAG State Diagram 1 TEST-LOGIC RESET RUN TEST/IDLE Document Number: 249252 Revision Number: 006 Revision Date: 19-Jan-2006 ® Intel LXT385 Octal E1 S/H PCM Transceiver with JA 1 SELECT- CAPTURE- SHIFT-DR ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 9.4 JTAG Register Description The following paragraphs describe each of the registers represented in 9.4.1 Boundary Scan Register (BSR) The BSR is a shift register that provides access to all ...
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Table 48. Boundary Scan Register (BSR) (Sheet Pin Bit # I/O Type Signal 22 N/A 23 RNEG1 24 LOS1 25 TCLK0 26 TPOS0 27 TNEG0 28 RCLK0 29 RPOS0 30 N/A 31 RNEG0 32 LOS0 33 MUX ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 48. Boundary Scan Register (BSR) (Sheet Pin Bit # I/O Type Signal R/W 55 ALE MOT/INTL 58 TCLK5 59 TPOS5 ...
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Table 48. Boundary Scan Register (BSR) (Sheet Pin Bit # I/O Type Signal 86 N/A 87 RPOS6 88 RCLK6 89 TNEG6 90 TPOS6 91 TCLK6 92 MCLK 93 MODE ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Figure 17. Analog Test Port Application RTIP7 RRING7 TTIP7 TRING7 RTIP6 RRING6 TTIP6 TRING6 RTIP0 1K RRING0 1K AT2 AT1 98 JTAG Port ASR Register Transceiver 7 Transceiver 6 Transceiver ...
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Analog Port Scan Register (ASR) The ASR bit shift register used to control the analog test port at pins AT1, AT2. When the INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 9.4.5 Instruction Register (IR) The bit shift register that loads the instruction to be performed. The instructions are shifted LSB first. Table 51 shows the valid ...
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Electrical Characteristics The tables in this chapter specify the electrical characteristics of the LXT385 ransceiver. The specifications are guaranteed by test except, where noted, by design. The minimum and maximum values listed are guaranteed over the specified recommended operating ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 54 lists recommended values for LXT385 ransceiver operating conditions. Table 54. Recommended Operating Conditions Ambient operating temperature Average digital power supply current Output load at TTIP and TRING DC ...
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Table 55 lists power consumption values for the LXT385 ransceiver. ® Table 55. Intel LXT385 Transceiver Power Consumption Parameter TVCC Load 75Ω 3.3V 120Ω 75Ω 5.0V (1:2 trans- former) 120Ω 75Ω 5.0V (Low power - 1:1.17 trans- former) 120Ω 1. ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA The LXT385 transceiver dissipates power in two ways: • Power dissipation of the transceiver itself. • Load power dissipation on external resistors and capacitors. The maximum load power (current draw) ...
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Table 57 lists the DC characteristics for the LXT385 ransceiver. Table 57. DC Characteristics Parameter Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage TTIP, TRING - output current HIgh-impedance tristate leakage current Input leakage current - ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 58 lists the AC characteristics for the LXT385 ransceiver transmitter. ® Table 58. Intel LXT385 Transceiver AC Transmitter Characteristics Parameter Pulse-Sequence Differences and Pulse-Width Ratio Difference between pulse sequences ...
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Table 59 lists the AC characteristics for the LXT385 ransceiver receiver. ® Table 59. Intel LXT385 Transceiver AC Receiver Characteristics Parameter Permissible cable attenuation Signal-to-noise interference margin, per ITU G.703, O.151 Data decision threshold - Relative to peak input voltage ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 11.0 Timing Characteristics This chapter discusses the following timing characteristics: • Section 11.1, “Intel® LXT385 Transceiver Timing” • Section 11.2, “Host Processor Mode - Parallel Interface Timing” — Section 11.2.1, ...
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Intel LXT385 Transceiver Timing Table 60 lists transmit timing characteristics for the LXT385 ransceiver. ® Table 60. Intel LXT385 Transceiver Transmit Timing Characteristics Parameter Master Clock Timing Master clock (MCLK) frequency Master clock tolerance Master clock duty cycle ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 61 lists receive timing characteristics for the LXT385 ransceiver. ® Table 61. Intel LXT385 Transceiver Receive Timing Characteristics Parameter Receive Clock Timing Receive clock-recovery capture range, relative to nominal ...
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Host Processor Mode - Parallel Interface Timing This sections gives timing characteristics and timing diagrams for both Intel Motorola processors. ® 11.2.1 Intel Processor - Parallel Interface Timing Table 62 lists read timing characteristics for the Intel ® Table ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Figure timing diagram for the Intel multiplexed interface, and a read cycle takes place. ® Figure 21. Intel Processor Non-Multiplexed Interface - Read Timing A4:0 ALE (Connected ...
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Figure timing diagram for the Intel multiplexed interface, and a read cycle takes place. ® Figure 22. Intel Processor Multiplexed Interface - Read Timing tVL ALE CS RD tSALR ADDRESS AD7-AD0 INT Tristate RDY Document Number: 249252 ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 63 lists write timing characteristics for the Intel ® Table 63. Intel Processor - Write Timing Characteristics Parameter Address setup time to latch Valid address latch pulse width Latch ...
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Figure timing diagram for the Intel multiplexed interface, and a write cycle takes place. ® Figure 23. Intel Processor Non-Multiplexed Interface - Write Timing A4:0 (Connected High) ALE CS WR D7:0 INT Tristate RDY Document Number: 249252 ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Figure timing diagram for the Intel multiplexed interface, and a write cycle takes place. ® Figure 24. Intel Processor Multiplexed Interface - Write Timing ALE tVL CS ...
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Motorola* Processor - Parallel Interface Timing Table 64 lists read timing characteristics for the Motorola processor. Table 64. Motorola Processor - Read Timing Characteristics Address setup time to address or data strobe Address hold time from address or data ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Figure timing diagram for the Motorola processor in the Host Processor mode, with a non- multiplexed interface, and a read cycle takes place. Figure 25. Motorola Processor ...
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Figure timing diagram for the Motorola processor in the Host Processor mode with a multiplexed interface, and a read cycle takes place. Figure 26. Motorola Processor Multiplexed Interface - Read Timing AS tSRW R/W CS tASDS DS ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Table 65 lists write timing characteristics for the Motorola processor. Table 65. Motorola Processor - Write Timing Characteristics Parameter Address setup time to address strobe Address hold time to address ...
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Figure timing diagram for the Motorola processor in the Host Processor mode, with a non- multiplexed interface, and a write cycle takes place. Figure 27. Motorola Processor Non-Multiplexed Interface - Write Timing A4:0 ADDRESS tSAS AS (Connected ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Figure timing diagram for the Motorola processor in the Host Processor mode, with a multiplexed interface, and a write cycle takes place. Figure 28. Motorola Processor Multiplexed ...
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Host Processor Mode - Serial Interface Timing Table 66 lists serial I/O timing for a Motorola or Intel a serial interface. Table 66. Serial I/O Timing Characteristics Rise/fall time any pin SDI to SCLK setup time SCLK to SDI ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Figure timing diagram for serial output from the Host Processor interface. Figure 30. Serial Output Timing CLKE = SCLK CS SDO CLKE ...
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Line-Interface-Unit Circuit Specifications Table 67 lists specifications for the LIU circuits with which the LXT385 ransceiver is designed to operate. (For a diagram of an LIU circuit to be used with the LXT385 ransceiver, Section 6.5, “Line-Interface Table 67. ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 13.0 Mask Specifications This chapter discusses the specifications for the mask into which the LXT385 ransceiver transmitter output pulses must fit. The mask specification has two parts. • Part 1 ...
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Jitter Performance This chapter includes tables and figures on jitter performance. For more information on jitter, see: • Section 6.6, “Jitter Attenuation” • Table 40 in Chapter 8.0, “Registers” Table 70 lists jitter attenuator characteristics for the LXT385 ransceiver. ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Figure 32 shows the typical LXT385 ransceiver jitter tolerance in comparison to the ITU G.823 standard. ® Figure 32. Intel LXT385 Transceiver Jitter Tolerance Compared to ITU G.823 1000 UI ...
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Figure 33 shows the typical jitter transfer performance for the LXT385 ransceiver in comparison to the ITU G.736 template. ® Figure 33. Intel LXT385 Transceiver Jitter Transfer Performance -10 dB -20 ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Figure 34 shows the typical jitter performance of the LXT385 ransceiver when it is used in ETSI CTR12/13 applications that place the LXT385 ransceiver in a system with other devices. ...
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Recommendations and Specifications • AT&T* - Technical Reference 62411 “Private Line Services - Description and Interface Specification”, December 1990. • European Telecommunications Standards Institute (ETSI) publications: — ETSI CTR12/13 - • TCTR 012 Reference DTR/NA-004001. Network Aspects (NA). ONP ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA • Office of Telecommunications (United Kingdom) publication: OFTEL OTR-001 Short Circuit Current Requirements • Telcordia* publications. (Telcordia was formerly known as Bellcore.) — GR-253-CORE SONET Transport Systems Common Generic Criteria ...
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Mechanical Specifications Figure 35. Dimensions for 144-Pin Low Octal Flat Package (LQFP) 144-Pin LQFP • Part Number LXT385LE • Extended Temperature Range (-40 D/2 E1/2 E1 Dimension ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA Figure 36. Dimensions for 160-Ball Plastic Ball Grid Array (BGA) 160-Pin PBGA • Part Number LXT385BE • Extended Temperature Range (-40 15.00 13.00 ±0.20 4.72 ±0.10 PIN #A1 CORNER PIN ...
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Top Label Markings Figure 37 shows a sample LQFP non-RoHS package for the LXT385 Transceiver. Notes contrast to the Pb-Free (RoHS-compliant) LQFP package, the non-RoHS-compliant package does not have the “e3” symbol in the last line of ...
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... Intel LXT385 Octal E1 S/H PCM Transceiver with JA 17.0 Product Ordering Information Table 71 lists product ordering information for the LXT385 Transceiver. ordering information matrix. Table 71. Product Ordering Information Product Number Revision DJLXT385LE.B1 WJLXT385LE.B1 136 Package Pin RoHS Type Count Compliant B1 LQFP 144 ...
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... H = QFP T = TQFP B = BGA C = CBGA E = TBGA K = HSBGA (BGA with heat slug Product Code xxxxx = 3-5 Digit alphanumeric IXA Product Prefix LXT = PHY layer device IXE = Switching engine IXF = Formatting device(MAC/Framer) IXP = Network processor Intel Package Designator Pb-Free Package Leaded WB HQFP HB WJ LQFP ...
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Intel LXT385 Octal E1 S/H PCM Transceiver with JA 19.0 Abbreviations and Acronyms Table 72 lists abbreviations and acronyms and their meanings. Table 72. Abbreviations, Acronyms, and Meanings Abbreviation or Acronym AIS AMI BPV ESD FCS FIFO HDB3 I/O ...