WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 36

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

36
Intel
Table 8.
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Framer/Mapper Receive Signals (Sheet 2 of 2)
BPV7 /
BPV6 /
BPV5 /
BPV4 /
BPV3 /
BPV2 /
BPV1 /
BPV0 /
RDATA7 /
RDATA6 /
RDATA5 /
RDATA4 /
RDATA3 /
RDATA2 /
RDATA1 /
RDATA0 /
1. AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output.
Signal
Name
RNEG7
RNEG6
RNEG5
RNEG4
RNEG3
RNEG2
RNEG1
RNEG0
RPOS7
RPOS6
RPOS5
RPOS4
RPOS3
RPOS2
RPOS1
RPOS0
QFP
141
105
112
142
104
Pin
111
69
76
34
41
70
77
33
40
4
5
PBGA
M12
M13
Ball
C12
C13
A12
P12
A13
P13
M3
M2
A3
C3
P3
A2
C2
P2
Signal
Type
DO
DO
Receive Negative Data Output 7:0.
This signal description applies to both RNEG and RPOS in
bipolar I/O mode. When the LXT385 ransceiver is in the:
When MCLK is provided with a clocking signal:
When MCLK is high:
When MCLK is low:
NOTE: For pin functions involving unipolar mode, see the
Receive Positive Data Output 7:0.
For the RPOS description, see RNEG.
NOTE: For pin functions involving unipolar mode, see the
• Host processor mode, during an LOS condition, AIS
• Hardware mode, RNEG and RPOS remain active
• The LXT385 ransceiver enters clock-recovery mode.
• These signals are valid on the falling or rising edges of
• The LXT385 ransceiver enters data recovery mode.
• These signals are valid on the falling or rising edges of
• RNEG and RPOS can be placed in a high-impedance
can be inserted into the receive path. See the
description of the GCR register RAISEN bit, in
6.3.6, “Receive Alarm Indication Signal (RAIS) Enable”
on page
during an LOS condition.
RNEG[7:0] act as active-high bipolar Non Return to
Zero (NRZ) receive signal outputs.
• A High signal on RNEG corresponds to receipt of a
• A High signal on RPOS corresponds to receipt of a
RCLK, depending on the CLKE input. See the CLKE
pin description in
Signals” on page
RNEG[7:0] act as RZ data receiver outputs.
RCLK, depending on the CLKE input. See the CLKE
pin description in
Signals” on page
tristate with the MCLK pin. (For details, see MCLK in
Section 5.5, “Clocks and Clock-Related
negative pulse on RTIP/RRING.
positive pulse on RTIP/RRING.
BPV pin description.
RDATA pin description.
55.
Signal Description
Table 11, “Clocks and Clock-Related
43.
Table 11, “Clocks and Clock-Related
43.
Revision Date: 19-Jan-2006
Document Number: 249252
Revision Number: 006
Signals”.)
Section