WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 4

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Contents
7.0
8.0
9.0
10.0
11.0
4
6.7
6.8
6.9
6.10
Operating Mode Summary
7.1
7.2
7.3
7.4
7.5
Registers
8.1
8.2
8.3
JTAG Boundary Scan
9.1
9.2
9.3
9.4
Electrical Characteristics
Timing Characteristics
11.1
11.2
11.3
Loopbacks ........................................................................................................... 67
6.7.1
6.7.2
6.7.3
Transmit All Ones Operations ............................................................................. 70
6.8.1
6.8.2
6.8.3
Performance Monitoring ...................................................................................... 72
Intel
Interfacing with 5V Logic ..................................................................................... 74
Hardware Mode................................................................................................... 74
Hardware Mode Settings..................................................................................... 75
Host Processor Modes ........................................................................................ 76
7.4.1
7.4.2
Interrupt Handling................................................................................................ 79
7.5.1
7.5.2
7.5.3
Register Summary .............................................................................................. 80
Register Addresses ............................................................................................. 82
Register Descriptions .......................................................................................... 83
Overview ............................................................................................................. 91
Architecture ......................................................................................................... 91
TAP Controller..................................................................................................... 92
JTAG Register Description.................................................................................. 94
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
Intel
Host Processor Mode - Parallel Interface Timing.............................................. 111
11.2.1 Intel
11.2.2 Motorola* Processor - Parallel Interface Timing................................... 117
Host Processor Mode - Serial Interface Timing ................................................ 123
...................................................................................................................... 80
®
®
Hitless Protection Switching ...................................................................... 73
LXT385 Transceiver Timing .................................................................... 109
Analog Loopback ................................................................................... 67
Digital Loopback..................................................................................... 68
Remote Loopback .................................................................................. 69
TAOS Generation................................................................................... 70
TAOS Generation with Analog Loopback .............................................. 71
TAOS Generation with Digital Loopback................................................ 71
Host Processor Mode - Parallel Interface............................................... 76
Host Processor Mode - Serial Interface ................................................. 78
Interrupt Sources.................................................................................... 79
Interrupt Enable...................................................................................... 79
Interrupt Clear ........................................................................................ 79
Boundary Scan Register (BSR).............................................................. 94
Analog Port Scan Register (ASR) .......................................................... 99
Device Identification Register (IDR) ....................................................... 99
Bypass Register (BYR) .......................................................................... 99
Instruction Register (IR) ....................................................................... 100
®
Processor - Parallel Interface Timing ......................................... 111
............................................................................................. 91
......................................................................................... 108
.................................................................................... 101
................................................................................... 74
Revision Date: 19-Jan-2006
Document Number: 249252
Revision Number: 006
Datasheet