WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 7

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Datasheet
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
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Line Interface Unit Signals .................................................................................. 40
Clocks and Clock-Related Signals ...................................................................... 43
Configuration and Mode-Select Signals .............................................................. 45
Signal Loss and Line-Code-Violation Signals ..................................................... 47
Performance-Monitoring Selections with A3:0 Pins ............................................ 48
Power and Grounds ............................................................................................49
JTAG Analog Interface Test Signals ................................................................... 50
JTAG Digital Interface Test Signals .................................................................... 50
Component Values to Use with Transformer Circuit ........................................... 64
Transmitter Transformer Turns Ratio Selection .................................................. 64
Intel
and Loopback...................................................................................................... 75
Host Processor Mode - Parallel Interface Selections .......................................... 76
Intel
Register Bit Names ............................................................................................. 81
Register Addresses for Serial and Parallel Interfaces......................................... 82
ID Register, ID - 00h............................................................................................83
Analog Loopback Register, ALOOP - 01h...........................................................83
Remote Loopback Register, RLOOP - 02h ......................................................... 83
TAOS Enable Register, TAOS - 03h ................................................................... 83
LOS Status Monitor Register, LOS - 04h ............................................................ 84
DFM Status Monitor Register (05h) for Intel
LOS Interrupt Enable Register, LIE - 06h............................................................ 84
DFM Interrupt Enable Register, DIE (07h) for Intel
LOS Interrupt Status Register, LIS - 08h............................................................. 84
DFM Interrupt Status Register, LIS - 09h ............................................................ 84
Reset Register, RES - 0Ah.................................................................................. 85
Performance-Monitoring Register, MON - 0Bh ................................................... 86
Digital Loopback Register, DL - 0Ch ................................................................... 87
LOS/AIS Criteria Selection Register, LACS - 0Dh .............................................. 87
Automatic TAOS Select Register, ATS - 0Eh...................................................... 87
Global Control Register, GCR - 0Fh.................................................................... 88
Pulse Shaping Indirect Address Register, PSIAD (10h)...................................... 89
Pulse Shaping Data Register, PSDAT (11h) for Intel
Output Enable Register, OER - 12h .................................................................... 89
AIS Status Monitor Register, AIS - 13h ............................................................... 89
AIS Interrupt Enable Register, AISIE - 14h ......................................................... 89
AIS Interrupt Status Register, AISIS - 15h .......................................................... 90
TAP State Description ......................................................................................... 92
Boundary Scan Register (BSR)........................................................................... 94
Analog Port Scan Register (ASR) .......................................................................99
Device Identification Register (IDR) .................................................................... 99
Instruction Register (IR) .................................................................................... 100
JTAG Timing Characteristics............................................................................. 100
Absolute Maximum Ratings............................................................................... 101
Recommended Operating Conditions ............................................................... 102
Intel
Load
DC Characteristics ............................................................................................ 105
Intel
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LXT385 Transceiver Register Summary ................................................... 80
LXT385 Transceiver Hardware Mode Settings for Receive, Transmit,
LXT385 Transceiver Power Consumption............................................... 103
LXT385 Transceiver AC Transmitter Characteristics .............................. 106
Power Consumption ............................................................................... 104
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LXT385 Transceiver .................... 84
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LXT385 Transceiver.......... 84
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LXT385 Transceiver ...... 89
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