WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 31

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Table 7.
Microprocessor-Standard Bus and Interface Signals (Sheet 2 of 3)
CS
D7
D6
D5
D4
D3
D2
D1
D0
DS
INT
RD
1. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. OD: Open Drain
/ LOOP7
/ LOOP6
/ LOOP5
/ LOOP4
/ LOOP3
/ LOOP2
/ LOOP1
/ LOOP0
/ JASEL
/ SDI / WR
/ R/W
Signal
Name
QFP
Pin
87
28
27
26
25
24
23
22
21
84
82
85
PBGA
Ball
K13
J14
J13
J11
H2
H3
G2
K1
J1
J2
J3
J4
Signal
Type
DI/O
OD,
DO
DI
DI
DI
Chip Select (Active Low) Input.
When the LXT385 ransceiver is in the:
(Parallel) Data Bus Input/Output 7:0.
When the LXT385 ransceiver is in the:
Data Strobe (Active Low) Input.
When the LXT385 ransceiver is in the:
For other pin functions, see SDI and WR.
Interrupt (Active Low, Open Drain).
INT is an active low, maskable, open drain output. If either an AIS
or LOS interrupt enable bit is enabled, INT goes low to flag the
host processor that the status of LXT385 ransceiver registers
changed state.
The host processor INT input must be set for level triggering.
(For information on the LOS interrupt enable, see
information on the AIS interrupt enable, see
interrupt details, see
INT requires an external 10kΩ pull-up resistor.
Read Enable (Active Low) Input.
When the LXT385 ransceiver is in the:
For other pin functions, see R/W.
• Host Processor mode, CS is used to select a specific
• Hardware mode, CS functions as JA Select (JASEL). (See
• Host Processor mode with a parallel interface that is:
• Host processor mode with a serial interface, D7:0 must be
• Hardware mode, the D7:0 pins function as LOOP7:0. (See
• Host Processor mode using a Motorola processor, DS acts
• Hardware mode, DS must be connected to ground.
• Host Processor mode using an Intel
• Hardware mode, RD must be connected to ground.
Intel
LXT385 ransceiver device so the host processor can
communicate with the registers of thatLXT385 ransceiver.
JASEL in
Signals”.)
• Non-multiplexed, D7:0 function as a bi-directional 8-bit
• Multiplexed, D7:0 carry both bi-directional 8-bit data and
grounded.
LOOP7:0 in
as a data strobe.
functions as a read enable.
data port.
the 8 least-significant address lines.
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Section 5.6, “Configuration and Mode-Select
Section 5.4, “Line Interface Unit
Section 7.5, “Interrupt
Signal Description
®
processor, RD
Handling”).
Table
Signals”.)
Table
45. For
31. For
31