WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 110

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

110
Intel
Table 61. Intel
Figure 20. Intel
®
LXT385 Octal E1 S/H PCM Transceiver with JA
RPOS
RNEG
RPOS
RNEG
RCLK
Table 61
Figure 20
Receive Clock Timing
Receive clock-recovery capture range, relative
to nominal frequency
Receive clock duty cycle
Receive clock pulse width
Receive clock pulse width low time
Receive clock pulse width high time
RCLK, RPOS, RNEG Timing
RPOS/RNEG to RCLK rising setup time
RCLK rising to RPOS/RNEG hold time
RPOS/RNEG pulse width (MCLK = high)
Rise/fall time
Delay time between RPOS/RNEG and RCLK
1. RCLK duty cycle widths vary depending on extent of received pulse jitter displacement. Maximum and
2. Clock recovery is disabled in this mode.
3. For all digital outputs.
4. If MCLK = high, the receive PLLs are replaced by a simple EXOR circuit.
minimum RCLK duty cycles are for worst-case jitter conditions (0.2 UI displacement, per ITU G.823).
®
®
LXT385 Transceiver Receive Timing Characteristics
LXT385 Transceiver - Receive Timing
lists receive timing characteristics for the LXT385 ransceiver.
CLKE = 0
is a receive timing diagram for the LXT385 ransceiver.
CLKE = 1
3
Parameter
tPWH
tSUR
1
1
tPW
2
tPWL
tSUR
tHR
Sym.
t
t
t
t
PWH
PWL
SUR
t
PW
HR
Min.
447
203
203
200
200
200
40
20
Typ.
±80
488
244
244
244
244
244
50
tHR
Max.
529
285
285
300
60
5
Unit
ppm
ns
ns
ns
ns
ns
ns
ns
ns
%
Revision Date: 19-Jan-2006
Document Number: 249252
MCLK = ±100 ppm
C
MCLK = high
Load
Revision Number: 006
Test Condition
= 15 pF
4