WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 99

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WJLXT385LE.B1

Manufacturer Part Number
WJLXT385LE.B1
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of WJLXT385LE.B1

Lead Free Status / RoHS Status
Supplier Unconfirmed
9.4.2
9.4.3
9.4.4
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Table 49. Analog Port Scan Register (ASR)
Table 50. Device Identification Register (IDR)
Analog Port Scan Register (ASR)
The ASR is a 5 bit shift register used to control the analog test port at pins AT1, AT2. When the
INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects to
the ASR output. After 5 TCK rising edges, a 5 bit control code is loaded into the ASR. Data into
the ASR is shifted in LSB first.
Table 49
Device Identification Register (IDR)
The IDR register provides access to the manufacturer number, part number and the LXT385
ransceiver revision. The register is arranged per IEEE 1149.1 and is represented in
into the IDR is shifted in LSB first.
Bypass Register (BYR)
The Bypass Register is a 1 bit register that allows direct connection between the TDI input and the
TDO output.
ASR Control Code
10101
10100
10010
10001
10000
11101
11100
11011
11010
11001
11000
10111
10110
10011
31 - 28
27 - 12
11111
11110
11 - 1
Bit #
shows the 16 possible control codes and the corresponding operation on the analog port.
0
AT1 Forces Voltage To:
Revision number
Part number
Manufacturer number
Set to “1”
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
Comments
Intel
AT2 Senses Voltage From:
®
LXT385 Octal E1 S/H PCM Transceiver with JA
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
Table
50. Data
99

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