WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 77

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7.4.1.1
7.4.1.2
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Host Processor Mode - Parallel Interface, Motorola* Processor
The Motorola processor interface is selected by asserting the LXT385 ransceiver MOT/INTL pin
low. The R/W signal indicates if a data transfer is to be a read or write. The DS signal is the timing
reference for all data transfers and typically has a duty cycle of 50%. When the Motorola processor
attempts to:
When a Motorola processor is used, CS and DS can be connected. Both read and write cycles
require the CS signal to be low and the Motorola processor to actively drive the address pins. The
LXT385 ransceiver supports a:
Host Processor Mode - Parallel Interface, Intel
The Intel
Both the read and write cycles require CS to be low. When the Intel
The LXT385 ransceiver supports a:
•
•
•
•
•
•
•
•
Read data from the LXT385 ransceiver, it asserts R/W high on the falling edge on DS, and the
LXT385 ransceiver drives the data bus.
Write data to the LXT385 ransceiver, it asserts R/W low on the rising edge on DS, and the
Motorola processor drives the data bus.
Non-multiplexed Motorola processor parallel interface when MUX is asserted low. In non-
multiplexed mode, the falling edge of DS is used to latch the address information on the
address bus, and AS must be connected high.
Multiplexed Motorola processor parallel interface when MUX is asserted high. The address on
the multiplexed address data bus is latched into the LXT385 ransceiver on the falling edge of
AS.
Read data from the LXT385 ransceiver, it asserts RD low while WR is held high.
Write data to the LXT385 ransceiver, it asserts WR low while RD is held high.
Non-multiplexed Intel
multiplexed mode, ALE must be connected high and the address and data lines are separate.
Multiplexed Intel
mode, the falling edge of ALE latches the address.
®
processor interface is selected by asserting the LXT385 ransceiver MOT/INTL pin high.
®
processor parallel interface when MUX is asserted high. In the multiplexed
®
processor parallel interface when MUX is asserted low. In non-
Intel
®
LXT385 Octal E1 S/H PCM Transceiver with JA
®
Processor
®
processor attempts to:
77