WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 113

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WJLXT385LE.B1

Manufacturer Part Number
WJLXT385LE.B1
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of WJLXT385LE.B1

Lead Free Status / RoHS Status
Supplier Unconfirmed
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
AD7-AD0
Figure 22. Intel
RDY
ALE
INT
CS
RD
Figure 22
multiplexed interface, and a read cycle takes place.
Tristate
tSALR
®
Processor Multiplexed Interface - Read Timing
is a timing diagram for the Intel
tVL
ADDRESS
tDRDY
tHALR
tSLR
tSCSR
tPRD
®
Intel
processor in the Host Processor mode, with a
tVRDY
tVRD
®
LXT385 Octal E1 S/H PCM Transceiver with JA
DATA OUT
tHSCR
tDRDY
tZRD
tINT
Tristate
tRDYZ
113

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