WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 112

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WJLXT385LE.B1

Manufacturer Part Number
WJLXT385LE.B1
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of WJLXT385LE.B1

Lead Free Status / RoHS Status
Supplier Unconfirmed
112
Intel
D7:0
Figure 21. Intel
A4:0
ALE
®
RDY
INT
CS
RD
LXT385 Octal E1 S/H PCM Transceiver with JA
Tristate
(Connected High)
Figure 21
multiplexed interface, and a read cycle takes place.
®
Processor Non-Multiplexed Interface - Read Timing
is a timing diagram for the Intel
tDRDY
tSCSR
tPRD
tSAR
®
ADDRESS
tVRDY
processor in the Host Processor mode, with a non-
tVRD
DATA OUT
tDRDY
tZRD
tHCSR
tHAR
tINT
Revision Date: 19-Jan-2006
Document Number: 249252
Revision Number: 006
Tristate
tRDYZ

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