WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 72

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WJLXT385LE.B1

Manufacturer Part Number
WJLXT385LE.B1
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of WJLXT385LE.B1

Lead Free Status / RoHS Status
Supplier Unconfirmed
6.9
72
Intel
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Note:
Performance Monitoring
The LXT385 ransceiver can be set for either one of the following configurations:
The LXT385 ransceiver can be configured to monitor the performance of either (1) one of the line-
side receivers 1 through 7 or (2) one of the line-side transmitters 1 through 7. The configuration can
be performed using either the Hardware mode (see
Code-Violation
Performance Monitoring through Clock and Data Recovery. Performance monitoring of either
(1) analog inputs to channels 1 through 7 or (2) analog outputs from any one of channels 1 through
7 can be accomplished through clock and data recovery as follows.
Performance Monitoring through Remote Loopback. Performance monitoring of either
(1) analog line inputs RTIP/RRING to any one of channels 1 through 7 or (2) analog line outputs
TTIP/TRING from any one of channels 1 through 7 can be accomplished through remote loopback
as follows:
A benefit of performance-monitoring is that the monitored signal can be sent to channel 0, where it
can be used as a timing reference clock.
1. As shown in
2. The line signal from the channel selected can then be observed digitally at RCLK0/RPOS0/
1. Configure the LXT385 ransceiver as shown
2. The monitored channel and channel 0 output the same data. By connecting the channel 0
All eight channels 0 through 7 operating as regular transceivers
Channels 1 through 7 operating as regular transceivers and the channel 0 transceiver
configured for non-intrusive performance monitoring of one of the other channels, per ITU-T
G.722
selected for monitoring is processed by the channel 0 transceiver clock and data recovery.
RNEG0. Channel 0 displays the appropriate LOS state for the line signal of the channel
selected, both in transmit and receive directions.
Loopback”. (TCLK must be active for remote loopback to operate.)
output data (TTIP0/TRING0) to standard test equipment, the line signal from the channel
selected can be monitored.
Signals”) or the Host Processor mode (see
Figure 1
in
Chapter 2.0, “Product
inFigure 10
Table 14
Summary”, the analog input from the channel
Table 36
in
in
Section 5.7, “Signal Loss and Line-
Section 6.7.3, “Remote
in
Chapter 8.0,
Revision Date: 19-Jan-2006
Document Number: 249252
Revision Number: 006
“Registers”).

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