WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 59

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Caution:
In the Hardware mode, if TCLK is connected high 16 consecutive MCLK clock cycles and MCLK
is:
When the pulse-shaping circuit is disabled, it is possible to overheat and damage the LXT385
ransceiver by leaving transmit inputs connected high continuously. For example, if a
programmable ASIC is used in a system that uses the LXT385 ransceiver, the ASIC outputs might
be left high until the ASIC is fully programmed. To prevent damage to the LXT385 ransceiver, use
either one of the following practices:
Set LEN2-0 to 000.
•
•
•
•
•
•
Not supplied (or ‘low’), the transmit pulse-shaper circuit shown in
is, disabled). In this case, TPOS and TNEG control the pulse width and polarity on TTIP and
TRING.
Supplied, the driver enters into a special mode known as Transmit All Ones, or ‘TAOS’. For
more information on the TAOS mode, see
Chapter 8.0,
Apply a clock to one of these signals: TPOS, TNEG, TCLK, or MCLK.
Set one of these signals low: TPOS, TNEG, TCLK, or OE.
In hardware mode, pins LEN0-2 determine the pulse shaping.
In host processor mode, see
LXT385 Transceiver” on page
“Registers”.
Table 42, “Pulse Shaping Data Register, PSDAT (11h) for Intel®
89.
Intel
Section 6.8, “Transmit All Ones Operations”
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Figure 1
is bypassed (that
and
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