WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 52

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.1
6.2
52
Intel
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Note:
Note:
Functional Overview
The LXT385 ransceiver is a fully integrated octalline interface unit designed for 2.048 Mbps
short-haul applications. (For a block diagram, see
The LXT385 ransceiver can be controlled either by a ‘Hardware mode’ that uses hard-wired pins
or by a ‘Host Processor mode’, which uses either a serial or parallel host processor interface that is
controlled in software. (For more information on selecting an operating mode, see
Section 4.1, “Operating Mode Multi-Function
Each transceiver front end interfaces with four lines: one pair of two lines for transmit, and one pair
of two lines for receive. These two pairs make up a digital data loop for full-duplex transmission.
The TCLK pin provides the transmitter timing reference, and the MCLK pin provides the receiver
reference clock. The LXT385 ransceiver is designed to operate without any reference clock when it
is used as an analog front end (that is, for data recovery in the receiver path and as a line driver in
the transmit path). MCLK is mandatory if on-chip clock recovery is required.
MCLK should be true to the recovered clock of the incoming data. It should be only
plesiochronous to MCLK.
All eight clock-recovery circuits share the same reference clock defined by the MCLK input signal.
(For details on MCLK, see
Initialization and Reset
Initialization for theLXT385 ransceiver occurs as follows:
For more information related to reset, see
Interface”.
1. During power-up, the LXT385 ransceiver is in an unknown state until the power supply
2. A write to the reset register (RES,
reaches approximately 70% of VCC. Also during power-up, an initial reset sets all registers to
their default values and resets the status and state machines for the LOS detector circuit.
(Between 50 and 70% of VCC, the LXT385 ransceiver is in a critical zone. For more
information about this critical zone, see the application note on slow power-up rise time,
referenced in
LXT385 ransceiver registers to their default values. When the reset cycle occurs:
b. In all other modes, the reset cycle is 1 microsecond long.
a. In the Intel
Section 1.3, “Related
®
processor non-multiplexed mode, the reset cycle is 2 microseconds long.
Table 11
in
Table
Section 5.5, “Clocks and Clock-Related
Documents”.)
Section 7.4.1, “Host Processor Mode - Parallel
35) initiates a reset cycle that results in setting all
Pins”.)
Figure
1.)
Revision Date: 19-Jan-2006
Document Number: 249252
Signals”.)
Revision Number: 006
Table 3
in