WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 76

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7.4
7.4.1
76
Intel
Table 21. Host Processor Mode - Parallel Interface Selections
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Note:
Host Processor Modes
When the MODE pin is connected high, the following Host Processor modes are available.
Host Processor Mode - Parallel Interface
The parallel interface (listed in
used to control configuration of the LXT385 ransceiver and to report the status of various
operations. The LXT385 ransceiver has a flexible, generic 8-bit parallel host processor interface
designed to support both non-multiplexed and multiplexed address/data bus systems for both
Motorola bus and Intel
selected with the pins MODE, MOT/INTL, and MUX.
The Host Processor mode parallel interface includes an address bus (A4:0) and a data bus (D7:0)
for non-multiplexed operation and an 8-bit address/data bus for multiplexed operation. The
LXT385 ransceiver has a 5-bit address bus and provides 22 user-accessible 8-bit registers for
configuration, alarm monitoring, and control of the LXT385 ransceiver.
Control signals that the LXT385 ransceiver and host processors have in common include ACK/
RDY, ALE, CS, DS, INT, RD, R/W, and WR. An internal wait-state generator controls the ACK/
RDY handshake output signal, which is compatible with both Motorola and Intel
When the processor interface selected is for a:
When an Intel
write-cycle timing operates that involves the use of Register 0Ah, the reset register. At the start of
the write cycle, the RDY line remains high instead of signaling the completion of the write cycle
with a transition to a low state. The overall duration of the reset cycle from when the signal on CS
is low to the completion of the reset cycle is a total of 3 microseconds. As a result, upon writing to
Register 0Ah, allow a minimum of 2 microseconds of constant throughput delay before attempting
the next read/write operation. (For more information on the reset cycle, see
“Register
MODE
•
•
•
•
High
High
High
High
Section 7.4.1, “Host Processor Mode - Parallel Interface”
Section 7.4.2, “Host Processor Mode - Serial Interface”
Motorola processor and ACK is low, then during a:
Intel
— Read cycle, ACK indicates that valid information is on the data bus.
— Write cycle, ACK indicates the LXT385 ransceiver has accepted the write data from the
— Low, the LXT385 ransceiver indicates to the Intel
Motorola processor.
®
Descriptions”.)
processor and RDY is:
MOT/
INTL
High
High
Low
Low
®
processor is used with a non-multiplexed interface, there is one exception to how
MUX
High
High
Low
Low
®
bus topologies.
Host Processor mode, Motorola processor parallel interface, non-multiplexed
Host Processor mode, Motorola processor parallel interface, multiplexed
Host Processor mode, Intel
Host Processor mode, Intel
Table 3
in
Table 21
Section 4.1, “Operating Mode Multi-Function
lists the four parallel interface modes that can be
®
®
processor parallel interface, non-multiplexed
processor parallel interface, multiplexed
Interface Selected
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processor a bus cycle is in progress.
Table 35
Revision Date: 19-Jan-2006
Document Number: 249252
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Revision Number: 006
processors.
in
Section 8.3,
Pins”) is