PIC18F65K90T-I/MR Microchip Technology, PIC18F65K90T-I/MR Datasheet - Page 205

• Manufacturer Part Number: PIC18F65K90T-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

15.2
Timer3, Timer5 and Timer7 can operate in these
modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
FIGURE 15-1:
 2009-2011 Microchip Technology Inc.
TxGSS<1:0>
TxG
From TMR(x + 1)
Match PR(x + 1)
From Comp. 1
Output
From Comp. 2
Output
Note 1:
Timer3/5/7 Operation
2:
3:
SOSCEN
TxGPOL
The ST buffer is high-speed type when using TxCKI.
Timerx registers increment on the rising edge.
Synchronization does not operate while in Sleep.
SOSCO
SOSCI
TxCKI
Set Flag bit
TMRxIF on
Overflow
00
10
11
01
TIMER3/5/7 BLOCK DIAGRAM
TMRxON
TxGTM
TMRxH
TxOSC
EN
OUT
TMRx
(1)
TxG_IN
(2)
R
D
CK
TMRxL
Q
Q
1
0
TMRxCS<1:0>
0
1
TxGGO/TxDONE
Q
Internal
Internal
F
OSC
Clock
Clock
F
OSC
EN
/4
PIC18F87K90 FAMILY
D
The operating mode is determined by the clock select
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
are cleared (= 00), Timer3/5/7 increments on every inter-
nal instruction cycle (F
Timer3/5/7 clock source is the system clock (F
when it is ‘10’, Timer3/5/7 works as a counter from the
external clock on the TxCKI pin (on the rising edge after
the first falling edge) or the SOSC oscillator.
Single Pulse
Acq. Control
10
01
00
TxCLK
TxGSPM
TxCKPS<1:0>
TxSYNC
Prescaler
1, 2, 4, 8
TMRxON
0
1
2
0
1
Internal
F
OSC
Clock
TxGVAL
OSC
/2
TMRxGE
Q1
Synchronize
Synchronized
/4). When TMRxCSx = 01, the
Clock Input
Interrupt
D
EN
Sleep Input
det
det
Q
(3)
DS39957D-page 205
Data Bus
RD
T3GCON
Set
TMRxGIF
OSC
), and