PIC18F65K90T-I/MR Microchip Technology, PIC18F65K90T-I/MR Datasheet - Page 483

• Manufacturer Part Number: PIC18F65K90T-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2009-2011 Microchip Technology Inc.
Q Cycle Activity:
After Instruction:
operation
Decode
No
PC = TOS
Q1
operation
operation
Return from Subroutine
RETURN {s}
s  [0,1]
(TOS)  PC;
if s = 1 ,
(WS)  W,
(STATUSS)  STATUS,
(BSRS)  BSR,
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the Program Counter. If
‘s’= 1 , the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, STATUS and BSR. If
‘s’ = 0 , no update of these registers
occurs.
1
2
RETURN
0000
No
No
Q2
0000
operation
Process
Data
No
Q3
0001
from stack
operation
POP PC
No
Q4
001s
PIC18F87K90 FAMILY
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
Rotate Left f through Carry
The contents of register ‘f’ are rotated
0  f  255
d  [ 0,1 ]
a  [ 0,1 ]
(f<n>)  dest<n + 1 >,
(f<7>)  C,
(C)  dest<0>
C, N, Z
one bit to the left through the Carry flag.
If ‘d’ is ‘ 0 ’, the result is placed in W. If ‘d’
is ‘ 1 ’, the result is stored back in register
‘f’.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f  95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
register ‘f’
=
=
=
=
=
RLCF
Read
0011
RLCF
Q2
1110 0110
0
1110 0110
1100 1100
1
C
f {,d {,a}}
01da
Process
Data
REG, 0, 0
Q3
register f
DS39957D-page 483
for details.
ffff
destination
Write to
Q4
ffff