PIC18F65K90T-I/MR Microchip Technology, PIC18F65K90T-I/MR Datasheet - Page 60

• Manufacturer Part Number: PIC18F65K90T-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
4.4.3
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode
provides controllable power conservation during Idle
periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. To maintain software
compatibility with future devices, it is recommended
that SCS0 also be cleared, though its value is ignored.
The INTOSC multiplexer may be used to select a
higher clock frequency by modifying the IRCF bits
before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC/MFIOSEL bit is set, the INTOSC output is
enabled. The HFIOFS/MFIOFS bits become set, after
the INTOSC output becomes stable after an interval of
T
on the HFIOFS/MFIOFS bits, see
Clocks to the peripherals continue while the INTOSC
source stabilizes. The HFIOFS/MFIOFS bits will
remain set if the IRCF bits were previously at a non-
zero value or if INTSRC was set before the SLEEP
instruction was executed and the INTOSC source was
already stable. If the IRCF bits and INTSRC are all
clear, the INTOSC output will not be enabled, the
HFIOFS/MFIOFS bits will remain clear and there will be
no indication of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
of T
wake event, the CPU begins executing code clocked
by the INTOSC multiplexer. The IDLEN and SCS bits
are not affected by the wake-up. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
DS39957D-page 60
IOBST
CSD
(Parameter 38,
(Parameter 38,
RC_IDLE MODE
Table
Table
31-10). (For information
31-10), following the
Table
4-3.)
consumption to an absolute minimum. In this state, the
peripheral are also disabled, so writes to those registers
peripheral modules have a corresponding PMD bit.
registers have bits associated with each module for
disabling or enabling a particular peripheral.
4.5
Idle mode allows users to substantially reduce power
consumption by stopping the CPU clock. Even so,
peripheral modules still remain clocked, and thus,
consume power. There may be cases where the
application needs what this mode does not provide: the
allocation of power resources to the CPU, processing
with minimal power consumption from the peripherals.
PIC18F87K90 family devices address this requirement
by allowing peripheral modules to be selectively
disabled,
consumption. This can be done with two control bits:
• Peripheral Enable bit, generically named XXXEN –
• Peripheral Module Disable (PMD) bit, generically
Disabling a module by clearing its XXXEN bit disables
the module’s functionality, but leaves its registers
available to be read and written to. This reduces power
consumption, but not by as much as the second
approach.
Most peripheral modules have an enable bit.
In contrast, setting the PMD bit for a module disables all
clock sources to that module, reducing its power
control and status registers associated with the
have no effect and read values are invalid. Many
There are four PMD registers in the PIC18F87K90 family
devices: PMD0, PMD1, PMD2 and PMD3. These
Located in the respective module’s main control
register
named XXXMD – Located in one of the PMDx
Control registers (PMD0, PMD1, PMD2 or PMD3)
Selective Peripheral Module
Control
reducing
 2009-2011 Microchip Technology Inc.
or
eliminating
their
power