PIC18F65K90-I/MR Microchip Technology, PIC18F65K90-I/MR Datasheet - Page 342

• Manufacturer Part Number: PIC18F65K90-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
21.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(T
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for T
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into an inactive state
(Figure
21.4.12.1
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 21-25:
FIGURE 21-26:
DS39957D-page 342
BRG
) and the SCLx pin is deasserted (pulled high).
21-25).
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SCLx
SDAx
Note: T
Sequence
SSPxIF
Note: T
Write to SSPxCON2,
SDAx
SCLx
Falling Edge of
9th Clock
BRG
Acknowledge Sequence Starts Here,
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
= one Baud Rate Generator period.
ACK
= one Baud Rate Generator period.
Set PEN
the End of Receive
Enable
ACKEN = 1, ACKDT = 0
SSPxIF Set at
Write to SSPxCON2,
BRG
T
T
bit,
BRG
; the SCLx pin
BRG
SDAx Asserted Low Before Rising Edge of Clock
to Set Up Stop Condition
D0
8
ACKEN
T
SCLx Brought High After T
BRG
Cleared in
P
T
Software SSPxIF Set at the End
BRG
SCLx = 1 for T
After SDAx Sampled High. P bit (SSPxSTAT<4>) is Set.
T
BRG
ACK
21.4.13
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to 0. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A T
cleared and the SSPxIF bit is set (see
21.4.13.1
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
of Acknowledge Sequence
PEN bit (SSPxCON2<2>) is Cleared by
T
BRG
Hardware and the SSPxIF bit is Set
9
BRG
BRG
, Followed by SDAx = 1 for T
BRG
STOP CONDITION TIMING
WCOL Status Flag
ACKEN Automatically Cleared
(Baud Rate Generator rollover count)
 2009-2011 Microchip Technology Inc.
Cleared in
Software
BRG
BRG
later, the PEN bit is
Figure
21-26).