PIC18F65K90-I/MR Microchip Technology, PIC18F65K90-I/MR Datasheet - Page 565

• Manufacturer Part Number: PIC18F65K90-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

Timing Diagrams
 2009-2011 Microchip Technology Inc.
A/D Conversion......................................................... 543
Automatic Baud Rate Calculation ............................. 358
Auto-Wake-up Bit (WUE) During Normal
Auto-Wake-up Bit (WUE) During Sleep .................... 365
Baud Rate Generator with Clock Arbitration ............. 336
BRG Overflow Sequence.......................................... 358
BRG Reset Due to SDAx Arbitration During
Brown-out Reset (BOR) ............................................ 528
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision During Start Condition
Bus Collision for Transmit and Acknowledge............ 343
Capture/Compare/PWM (ECCP1, ECCP2) .............. 532
CLKO and I/O ........................................................... 527
Clock Synchronization .............................................. 329
Clock/Instruction Cycle ............................................... 90
EUSART Asynchronous Reception .......................... 363
EUSART Asynchronous Transmission ..................... 360
EUSART Asynchronous Transmission
EUSART Synchronous Master Transmission ........... 367
EUSART Synchronous Transmission
EUSART/AUSART Synchronous Receive
Example SPI Master Mode (CKE = 0) ...................... 533
Example SPI Master Mode (CKE = 1) ...................... 534
Example SPI Slave Mode (CKE = 0) ........................ 535
Example SPI Slave Mode (CKE = 1) ........................ 536
External Clock........................................................... 525
Fail-Safe Clock Monitor (FSCM) ............................... 446
First Start Bit Timing ................................................. 337
Full-Bridge PWM Output ........................................... 262
Half-Bridge PWM Output .................................. 260, 267
High/Low-Voltage Detect Characteristics ................. 530
High-Voltage Detect Operation (VDIRMAG = 1)....... 404
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Acknowledge Sequence ..................................... 342
C Bus Data ............................................................. 538
C Bus Start/Stop Bits.............................................. 537
C Master Mode (7 or 10-Bit Transmission) ............ 340
C Master Mode (7-Bit Reception)........................... 341
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) ........... 326
C Slave Mode (10-Bit Reception, SEN = 1) ........... 331
C Slave Mode (10-Bit Transmission)...................... 327
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............. 322
C Slave Mode (7-Bit Reception, SEN = 1) ............. 330
C Slave Mode (7-Bit Transmission)........................ 324
C Slave Mode General Call Address Sequence
Operation .......................................................... 365
Start Condition .................................................. 345
Condition (Case 1) ............................................ 346
Condition (Case 2) ............................................ 346
(SCLx = 0)......................................................... 345
(Case 1) ............................................................ 347
(Case 2) ............................................................ 347
(SDAx Only) ...................................................... 344
(Back-to-Back) .................................................. 360
(Master/Slave) .................................................. 541
(Master/Slave) .................................................. 541
ADMSK = 01001).............................................. 325
ADMSK = 01011).............................................. 323
(7 or 10-Bit Addressing Mode) .......................... 332
PIC18F87K90 FAMILY
I
LCD Interrupt Timing in Quarter Duty Cycle Drive ... 298
LCD Reference Ladder Power Mode Switching ....... 283
LCD Sleep Entry/Exit When SLPEN = 1 or CS = 00 299
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 403
MSSP I
MSSP I
PWM Auto-Shutdown with Auto-Restart Enabled,
PWM Auto-Shutdown with Firmware Restart,
PWM Direction Change ............................................ 263
PWM Direction Change at Near 100%
PWM Output ............................................................. 248
PWM Output (Active-High) ....................................... 258
PWM Output (Active-Low) ........................................ 259
Repeated Start Condition ......................................... 338
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence............................. 366
Slave Synchronization .............................................. 309
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 308
SPI Mode (Slave Mode, CKE = 0) ............................ 310
SPI Mode (Slave Mode, CKE = 1) ............................ 310
Steering Event at Beginning of Instruction
Steering Event at End of Instruction
Synchronous Master Transmission
Synchronous Reception (Master Mode, SREN) ....... 369
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up
Timer Pulse Generation............................................ 234
Timer0 and Timer1 External Clock ........................... 531
Timer1 Gate Count Enable Mode............................. 193
Timer1 Gate Single Pulse Mode............................... 196
Timer1 Gate Single Pulse/Toggle
Timer1 Gate Toggle Mode........................................ 195
Timer3/5/7 Gate Count Enable Mode....................... 206
Timer3/5/7 Gate Single Pulse Mode......................... 208
Timer3/5/7 Gate Single Pulse/Toggle
Timer3/5/7 Gate Toggle Mode.................................. 207
Transition for Entry to Idle Mode ................................ 59
Transition for Entry to SEC_RUN Mode ..................... 55
Transition for Entry to Sleep Mode ............................. 58
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode................ 59
Transition for Wake from Sleep (HSPLL) ................... 58
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode...................................... 57
Type-A in 1/2 MUX, 1/2 Bias Drive........................... 288
2
C Stop Condition Receive or Transmit Mode......... 342
PxRSEN = 1 ..................................................... 266
PxRSEN = 0 ..................................................... 266
Duty Cycle ........................................................ 264
Timer (OST) and Power-up Timer (PWRT) ...... 528
V
(STRSYNC = 1)................................................ 270
(STRSYNC = 0)................................................ 270
(Through TXEN) ............................................... 368
Tied to V
Tied to V
(MCLR Tied to V
Combined Mode ............................................... 197
Combined Mode ............................................... 209
(INTOSC to HSPLL) ......................................... 444
PRI_RUN Mode.................................................. 57
PRI_RUN Mode (HSPLL) ................................... 55
DD
2
2
C Bus Data ................................................. 539
C Bus Start/Stop Bits .................................. 539
Rise > T
DD
DD
), Case 1 .......................................... 73
), Case 2 .......................................... 73
PWRT
DD
)............................................. 73
, V
DD
Rise T
DD
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,
PWRT
) ............... 72