PIC18F65K90-I/MR Microchip Technology, PIC18F65K90-I/MR Datasheet - Page 448

• Manufacturer Part Number: PIC18F65K90-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
TABLE 28-4:
28.6.1
The program memory may be read to, or written from,
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In Normal Execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘ 0 ’.
The EBTRn bits control table reads. For a block of user
memory with the EBTRn bit set to ‘ 0 ’, a table read
instruction that executes from within that block is allowed
to read. A table read instruction that executes from a
FIGURE 28-7:
DS39957D-page 448
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
30000Bh CONFIG6H
30000Ch CONFIG7L EBRT7
30000Dh CONFIG7H
Legend: Shaded cells are unimplemented.
Note 1:
File Name
TBLPTR = 0008FFh
Results: All table writes are disabled to Blockn whenever WRTn = 0
Register Values
This bit is available only on the PIC18F67K90 and PIC18F87K90 devices.
PROGRAM MEMORY
CODE PROTECTION
PC = 00BFFEh
PC = 003FFEh
SUMMARY OF CODE PROTECTION REGISTERS
TABLE WRITE (WRTn) DISALLOWED
WRT7
WRTD
CP7
Bit 7
CPD
—
(1)
(1)
(1)
EBRT6
WRT6
EBTRB
CP6
WRTB
Bit 6
CPB
(1)
(1)
(1)
EBTR5
WRT5
Program Memory
WRTC
CP5
Bit 5
—
—
TBLWT*
TBLWT*
(1)
(1)
(1)
EBTR4
WRT4
CP4
Bit 4
—
—
—
illustrate table write and table read protection.
location outside of that block is not allowed to read and
will result in reading ‘ 0 ’s. Figures
(1)
(1)
Note:
(1)
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
EBTR3
WRT3
Bit 3
CP3
—
—
—
Code protection bits may only be written
to a ‘ 0 ’ from a ‘ 1 ’ state. It is not possible to
write a ‘ 1 ’ to a bit in the ‘ 0 ’ state. Code
protection bits are only set to ‘ 1 ’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
programming
information.
.
 2009-2011 Microchip Technology Inc.
Configuration Bit Settings
EBTR2
WRT2
Bit 2
CP2
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
—
—
—
Refer
specification
EBTR1
WRT1
Bit 1
CP1
—
—
—
28-7
to
the
through
for
EBTR0
WRT0
Bit 0
CP0
device
—
—
—
more
28-9