PIC18F65K90-I/MR Microchip Technology, PIC18F65K90-I/MR Datasheet - Page 74

• Manufacturer Part Number: PIC18F65K90-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
5.7
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TO, PD, POR and BOR) are set or cleared differently in
TABLE 5-1:
DS39957D-page 74
Power-on Reset
RESET instruction
Brown-out Reset
Configuration Mismatch Reset
MCLR Reset during
power-managed Run modes
MCLR Reset during power-
managed Idle modes and
Sleep mode
MCLR Reset during full-power
execution
Stack Full Reset (STVREN = 1)
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
WDT time-out during full-power
or power-managed Run modes
WDT time-out during
power-managed Idle or Sleep
modes
Interrupt exit from
power-managed modes
Legend: u = unchanged
Note 1:
Reset State of Registers
Condition
When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Counter
Program
PC + 2
PC + 2
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(1)
CM
1
u
1
0
u
u
u
u
u
u
u
u
u
RI
1
0
1
u
u
u
u
u
u
u
u
u
u
RCON Register
different Reset situations, as indicated in
These bits are used in software to determine the nature
of the Reset.
Table 5-2
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets, and WDT wake-ups.
TO
1
u
1
u
1
1
u
u
u
u
0
0
u
PD
1
u
1
u
u
0
u
u
u
u
u
0
0
describes the Reset states for all of the
POR
0
u
u
u
u
u
u
u
u
u
u
u
u
 2009-2011 Microchip Technology Inc.
BOR
0
u
0
u
u
u
u
u
u
u
u
u
u
STKFUL STKUNF
STKPTR Register
0
u
u
u
u
u
u
1
u
u
u
u
u
Table
0
u
u
u
u
u
u
u
1
1
u
u
u
5-1.