ST92196A STMicroelectronics, ST92196A Datasheet - Page 111

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

8.4 OSDRAM CONTROLLER
8.4.1 Introduction
The OSDRAM Controller handles the interface be-
tween the Display Controller, the CPU and the OS-
DRAM.
The time slots are allocated to each unit in order to
optimize the response time.
The main features of the OSDRAM Controller are
the following:
8.4.2 Functional Description
The OSDRAM controller manages the data flows
between the different sub-units (display controller,
CPU) and the OSDRAM. A specific set of buses
(16-bit data, 9-bit addresses) is dedicated to these
data flows. The OSDRAM controller accesses
these buses in real time. The OSDRAM controller
has registers mapped in the ST9 register file.
Figure 50. Display Architecture Overview
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- OSDRAM CONTROLLER
Memory mapped in Memory Space (segment
22h of the MMU)
DMA access for Display control
Direct CPU access
RGB
FB
4 * 3 BITS
TRANSLUCENCY
ROM FONT
MATRIX
TSLU
DISPLAY CONTROLLER
ADDRESS (6+4 BITS)
DATA (8 BITS)
REGISTER BUSES
OSDRAM CONTROLLER
As this OSDRAM controller has also to deal with
TV real time signals (On-Screen-Display), a spe-
cific controller manages all exchanges:
– Its timing generator uses the same frequency
– Its controller can work in two TV modes:
– Its architecture gives priority to the TV real time
– Its controller enables a third operating mode
generator as the Display (Pixel frequency multi-
plier),
constraints: whenever there is access contention
between the CPU and the Display (shared
mode), the CPU is automatically forced in a
“wait” configuration until its request is served.
(stand-alone mode) which allows the application
to access the OSDRAM while the Display is
turned off. In this case, the OSDRAM controller
uses the CPU main clock.
OSD DISPLAY RAM
– Single mode: all time slots are dedicated to
– Shared mode: time slots are shared between
the CPU.
the CPU and the Display. The shared mode is
controlled by the Display controller.
OSD ADDRESS (9 BITS)
OSD DATA
CPU INTERFACE
MEMORY BUSES
ADDRESS (22 BITS)
(16 BITS)
DATA (8 BITS)