ST92196A STMicroelectronics, ST92196A Datasheet - Page 171

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

I
8.9.2 General Description
In addition to receiving and transmitting data, this
interface convert them from serial to parallel for-
mat and vice versa. The interface is connected,
through a multiplexer, to one I
data pin, SDAx, and by a clock pin, SCLx, where x
range value is 1 to 4.
It can be connected both with a standard I
and a Fast I
ware.
8.9.2.1 Mode Selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from inactive
slave to master after it generates a START condi-
tion and from master to inactive slave in case of ar-
bitration loss or a STOP generation, this allows
Multi-Master capability.
8.9.2.2 Communication Flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
Figure 69. I
171/268
- FOUR-CHANNEL I
2
C BUS INTERFACE (Cont’d)
2
2
SCL
SDA
C bus. This selection is made by soft-
C bus protocol
CONDITION
START
2
C BUS INTERFACE (I2C)
2
C bus among 4 by a
MSB
1
2
2
C bus
always begins with a start condition and ends with
a stop condition. Start condition is automatically
generated by the interface when the data register
is loaded by the slave address (see register de-
scription for further details). Stop condition is gen-
erated in master mode by writing by software in
the control register.
In Slave mode, the interface is capable of recog-
nising its own address (7-bit), and the General Call
address. The General Call address detection may
be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start condi-
tion is the address byte; it is always transmitted in
Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to
ure
The acknowledge may be enabled and disabled
by software.
The speed of the I
between Standard (15.625 - 100 kHz), Fast I
(100- 400 kHz), or Extended I
69.
8
ACK
9
2
C interface may be selected
CONDITION
STOP
2
C (500 - 800 kHz).
VR02119B
Fig-
2
C