ST92196A STMicroelectronics, ST92196A Datasheet - Page 158

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

OSD CONTROLLER (Cont’d)
SCAN LINE REGISTER (OSDSLR)
R251 - Read Only
Register Page: 42
Reset Value: xxxx xxxx (xxh)
Bits 7:0 = SL[7:0] Scan Line Counter Value
These bits indicate the current vertical position of
the TV beam.
The most significant bit SL8 of this counter is locat-
ed in the Flag Bit register OSDFBR (see below).
This counter starts from 0 at the top of the screen
(i.e. after the Vsync pulse) and is incremented by
HSYNC.
MUTE REGISTER (OSDMR)
R252 - Read/Write
Register Page: 42
Reset Value: 00xx x000
Bit 7 = ADMULT Address Multiply control bit
This bit, together with the ODEVN bit, controls the,
OSDRAM address generation. (Refer to the note
below for more details)
0: The CPU address is used to address the OS-
1: The CPU address is multiplied by 2 and the
ADMULT ODEVN
SL7
7
DRAM, i.e. the CPU address LSB bit is used as
OSDRAM address LSB.
ODEVN control bit is used as the OSDRAM LSB
address bit.
7
SL6
SL5
-
SL4
-
SL3
-
LSM2
SL2
LSM1 LSM0
SL1
SL0
0
0
- ON SCREEN DISPLAY CONTROLLER (OSD)
Note: This mechanism is intended for improved
software compatibility with the ST9296 when the
Display works in basic parallel mode; it allows to
do a buffer transfer to the OSDRAM using a basic
"ld memory-to-memory with post-increment" in-
struction; i.e.: ld(..)+, ('')+ to fill up the row buffer,
making an automatic reservation for the attribute
byte associated with the character.
Bit 6 = ODEVN Odd/Even address control bit
This bit controls the OSDRAM address LSB bit
when the ADMULT bit is high.
Refer to the ADMULT bit description for further de-
tails.
Bits 5:3 are reserved
Bits 2:0 = LSM[2:0] Line Start Mute value
These bits are used to program the mute duration
after the beginning of each TV line.
When the Display works in 1H mode the mute du-
ration can be adjusted in 2µs steps from 2 to 14 µs.
When the Display works in 2H mode the mute du-
ration can be adjusted in 1µs steps from 1 to 7 µs.
The LSM bits also define the HSY flag duration.
The Mute duration is expressed by the following
equation (the “1µs” is a frequency issued from the
crystal oscillator):
for 2H display mode: T
for 1H display mode: T
in both 1H/2H modes, if LSM[2:0] = 0 then T
Hsync width.
mute
mute
= LSM[2:0] * (1 µs)
= LSM[2:0] * 2*(1 µs)
158/268
mute
=