ST92196A STMicroelectronics, ST92196A Datasheet - Page 60

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

4.3 DMA TRANSACTIONS
The purpose of an on-chip DMA channel is to
transfer a block of data between a peripheral and
the Register File, or Memory. Each DMA transfer
consists of three operations:
– A load from/to the peripheral data register to/
– A post-increment of the DMA Address Register
– A post-decrement of the DMA transaction coun-
If the DMA transaction is carried out between the
peripheral and the Register File
register is required to hold the DMA Address, and
one to hold the DMA transaction counter. These
two registers must be located in the Register File:
the DMA Address Register in the even address
Figure 26. DMA Between Register File and Peripheral
from a location of Register File (or Memory) ad-
dressed through the DMA Address Register (or
Register pair)
(or Register pair)
ter, which contains the number of transactions
that have still to be performed.
PAGED REGISTERS
PERIPHERAL
DCPR
DAPR
DATA
IDCR
IVR
TABLE
DMA
FFh
F0h
EFh
E0h
DFh
(Figure
TRANSFERRED
REGISTER FILE
REGISTERS
REGISTERS
COUNTER
ADDRESS
ALREADY
26), one
SYSTEM
PAGED
DMA
DATA
DMA
ON-CHIP DIRECT MEMORY ACCESS (DMA)
register, and the DMA Transaction Counter in the
next register (odd address). They are pointed to by
the DMA Transaction Counter Pointer Register
(DCPR), located in the peripheral’s paged regis-
ters. In order to select a DMA transaction with the
Register File, the control bit DCPR.RM (bit 0 of
DCPR) must be set.
If the transaction is made between the peripheral
and Memory, a register pair (16 bits) is required
for the DMA Address and the DMA Transaction
Counter
be located in the Register File.
The DMA Transaction Counter is pointed to by the
DMA
(DCPR), the DMA Address is pointed to by the
DMA Address Pointer Register (DAPR),both
DCPR and DAPR are located in the paged regis-
ters of the peripheral.
000000h
000100h
Transaction
(Figure
SERVICE ROUTINE
END OF BLOCK
27). Thus, two register pairs must
ISR ADDRESS
INTERRUPT
MEMORY
Counter
Pointer
VECTOR
Register
TABLE
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