ST92196A STMicroelectronics, ST92196A Datasheet - Page 36

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

2.5 MEMORY MANAGEMENT UNIT
The CPU Core includes a Memory Management
Unit (MMU) which must be programmed to per-
form memory accesses (even if external memory
is not used).
The MMU is controlled by 7 registers and 2 bits
(ENCSR and DPRREM) present in EMR2, which
may be written and read by the user program.
These registers are mapped within group F, Page
21 of the Register File. The 7 registers may be
Figure 13. Page 21 Registers
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
DMASR
ISR
EMR2
EMR1
CSR
DPR3
DPR2
DPR1
DPR0
Page 21
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
MMU
EM
MMU
MMU
MODER
SSPHR
USPHR
USPLR
FLAGR
SSPLR
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
CICR
PPR
RP1
RP0
(default setting)
Bit DPRREM=0
Relocation of P[3:0] and DPR[3:0] Registers
sub-divided into 2 main groups: a first group of four
8-bit registers (DPR[3:0]), and a second group of
three 6-bit registers (CSR, ISR, and DMASR). The
first group is used to extend the address during
Data Memory access (DPR[3:0]). The second is
used to manage Program and Data Memory ac-
cesses during Code execution (CSR), Interrupts
Service Routines (ISR or CSR), and DMA trans-
fers (DMASR or ISR).
DMASR
EMR2
EMR1
DPR3
DPR2
DPR0
CSR
ISR
1
DEVICE ARCHITECTURE
MODER
USPHR
SSPHR
SSPLR
USPLR
FLAGR
P5DR
P4DR
DPR3
DPR2
DPR1
DPR0
CICR
PPR
RP1
RP0
Bit DPRREM=1
DMASR
EMR2
EMR1
P3DR
P2DR
P1DR
P0DR
CSR
ISR
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