ST92196A STMicroelectronics, ST92196A Datasheet - Page 174

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

I
Master Receiver
Following the address transmission and acknowl-
edgment, the master receives bytes from the SDA
line into the I2CDR register via the internal shift
register. After each byte the interface generates in
sequence:
– Acknowledge pulse according to the
– An interrupt is generated and the INT bit of the
Then read the I2CDR register to store the trans-
mitted data.
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the
SEND_ACK bit must be set just before reading the
second last data byte.
Master Transmitter
Following the address transmission and acknowl-
edgment, the master sends bytes from the I2CDR
register to the SDA line via the internal shift regis-
ter.
When the acknowledge bit is received, the inter-
face generates an interrupt and sets the INT bit of
the I2CSTR2 register.
The user can check the ACK_BIT bit of the
I2CSTR1 register in order to handle the transac-
tion properly.
2
C BUS INTERFACE (Cont’d)
SEND_ACK bit value,
I2CSTR2 register is set.
- FOUR-CHANNEL I
Closing a master communication
The master interface will generate a stop condition
on the bus when the user sets the STOP bit of the
I2CSTR1 register.
8.9.4 Interrupt Handling
To acknowledge interrupts generated by the I2C
interface, software must write any value in the
I2CDR register before leaving the I2C interrupt
subroutine. This is necessary in all modes includ-
ing slave or master receiver mode.
8.9.5 Error Cases
Each time an error occurs, an interrupt is generat-
ed. Then by checking the following bits, the user
can identify the problem:
– If the ERROR bit in the I2CSTR1 register is set,
– If the ARB_LOST bit, in the I2CSTR1 register is
Note: the ERROR bit has higher priority than the
ARB_LOST bit, so if ERROR is set, ARB_LOST
has to be ignored.
an illegal start or stop condition has been detect-
ed.
If the AFEN bit in the I2CCTR register is set, the
UNPROC, UNEXP, and MISP bits of the
I2CSTR2 register indicate what kind of illegal
condition has been detected.
set, an arbitration lost occurred on the bus.
2
C BUS INTERFACE (I2C)
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