ST92196A STMicroelectronics, ST92196A Datasheet - Page 178

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

I
DATA REGISTER (I2CDR)
R243 - Read/Write
Register Page: 44
Reset Value: 0000 0000(00h)
Bit 7:0 = SR[8:1] address or data byte
These bits contains the address or data byte load-
ed by software for sending on the I
also the address or data byte received on the bus
to be read by software.
When read, this register reflects the last byte
which has been transferred on the bus. Reading
this register is equivalent to reading the shift regis-
ter of the interface.
When written, the contents of this register will be
transferred into the shift register of the interface.
STATUS REGISTER 2 (I2CSTR2)
R244 - Read/Write (Bit 7:6),Read Only (Bit 5:0)
Register Page: 44
Reset Value: 0000 0000(00h)
Bit 7 = ISCEN Interrupt on Stop Condition Enable
bit
This bit determines if an interrupt is generated as
soon as a stop condition has been detected on the
bus.
0: No interrupt generated on a bus stop condition
1: An interrupt is generated on a bus stop condi-
Note: When the interface is involved in a transac-
tion, checking the ERROR status flag related to
the error detection allows to determine if the trans-
action has been successfully completed. This in-
terrupt can be useful for an interface waiting for a
“bus free” condition in order to become a master
as soon as possible. Checking the ACTIVE bit (in
the I2CSTR1 register) allows to correctly identify
an interrupt generated by a stop condition.
2
ISCEN SFEN SCLIN SDAIN INT UNPROC UNEXP MISP
SR8
C BUS INTERFACE (Cont’d)
7
7
tion.
SR7
SR6
SR5
SR4
SR3
2
C bus, and
SR2
SR1
0
0
- FOUR-CHANNEL I
Bit 6 = SFEN Spike Filter Enable bit
This bit enables or disables the spike filters on the
SDAx and SCLx inputs (x is 1 to 4).
0: spike filters disabled
1: spike filters enabled
Note: The length of a pulse identified as a spike
depends on the CPUCLK frequency used (CPU-
CLK frequencies from 10 to 20 Mhz allow to filter
pulses smaller than 100 to 40 ns).
Bit 5 = SCLIN SCL Input status bit
This read-only bit describes the current logic state
on the SCL bus.
It can be used to sample the signal on a newly se-
lected SCL bus for a quick determination concern-
ing the bus use and the bus clock frequency.
Bit 4 = SDAIN SDA Input status bit
This read-only bit describes the current logic state
on the SDA bus.
It can be used to sample the signal on a newly se-
lected SDA bus for a quick determination of the
state of this bus, prior starting a transaction.
Bit 3 = INT Interrupt status bit
This (read-only) bit indicates if an event has oc-
curred.
0: No interrupt requested or an interrupt resulting
1: The interface enters an interrupt state resulting
Bit 2 = UNPROC Unprocessed flag bit
This bit is useful in a multimaster mode system, to
solve conflicts between a “Repeated Start” or a
“Stop” condition and any bit of an address or data
byte from other concurrent masters.
0: No error occurred.
1: A master interface tried to generate a “Repeat-
Note: If this bit is set, it will automatically activate
the ERROR bit.
Note: This bit is only valid when the Advanced
Features Enable bit AFEN is set in the I2CCTR
register.
from a stop condition occurred.
from any error (bus error or arbitration loss) or
any byte transfer completed.
ed Start” or a “Stop” condition, which never oc-
curred.
2
C BUS INTERFACE (I2C)
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