ST92196A STMicroelectronics, ST92196A Datasheet - Page 123

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

OSD CONTROLLER (Cont’d)
Vertical & Horizontal Sync Pulse Inputs
A spike filter has been implemented on the vertical
Sync input. This circuit is inserted after internal po-
larity compensation of the VSYNC input signal
(see VPOL bit of the Delay Register, OSDDR). It
masks any spike on the vertical sync pulse with a
duration smaller than 3µs. The leading edge of the
VSYNC pin is affected by the vertical Sync pulse
cleaner. The VSYNC edges are internally delayed
by 3µs.
A Schmitt trigger provides noise immunity on the
horizontal Sync pulse input and will add a delay
between the deflection pulse and the effective
count start of the OSD line processing.
8.5.4.2 Field Detection in interlaced mode
For TV sets working in interlaced mode, the Dis-
play controller has to retrieve the field information
(some pixel information, like 18x26 matrix charac-
ters, rounding or fringe, is field based).
The Display is synchronized to HSYNC and
VSYNC inputs. The phase relationship of these
signals may be different from one chassis type to
another. Therefore, in order to prevent vertical
OSD jitter, some circuitry is implemented to pro-
vide a stable and secure field detection (OSD jitter
may appear if the rising edge of an external verti-
cal sync pulse coincides with that of an external
horizontal sync pulse). This circuitry delays the
vertical sync leading edge internally. The delay ap-
plied is software programmable through a 4-bit
value (refer to bit DBLS in the OSDDR register).
The field information is then extracted by appropri-
ate hardware logic.
8.5.4.3 Display Behaviour in 2H modes
The “2H” mode corresponds to a double scan dis-
play mode: the line frequency is doubled (to 31.5
123/268
- ON SCREEN DISPLAY CONTROLLER (OSD)
kHz) compared to the traditional 60 Hz field, 262.5
lines per field. This mode requires doubling the
pixel frequency and also adjusting some timing op-
erations (refer to
8.5.4.2).
This feature is controlled by the DBLS bit in the
OSDER register.
The double scan may be used in interlaced mode
(100/120 Hz field frequency) or in progressive
scanning (“non-interlaced” mode, 50/60 Hz field
frequency).
This feature is enabled by the NIDS bit in the OS-
DER register.
RGB-FB Line Start Mute
The R, G, B & FB outputs are muted after each
horizontal Sync pulse received on the HSYNC pin.
The mute duration is controlled by software
through a 3-bit value; these bits are called
“LSM(2:0)” and are located in the Mute register
OSDMR.
When the Display works in 1H mode (bit DBLS re-
set), the mute duration can be adjusted in 2µs
steps from 2 to 14 µs. When the Display works in
2H mode (bit DBLS set), the mute duration can be
adjusted in 1µs steps from 1 to 7 µs.
When the 3-bit mute value is “zero”, the R, G, B &
FB display outputs are muted during the duration
of the horizontal Sync pulse received on the
HSYNC pin.
For more details, refer to the DBLS bit in the OS-
DER and the LSM bits in the OSDMR register.
The HSY bit in the OSDFBR register provides an
image of the mute.
Section 8.5.4.1
and
Section