ST92196A STMicroelectronics, ST92196A Datasheet - Page 169

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

8.8 IR PREPROCESSOR (IR)
8.8.1 Functional Description
The IR Preprocessor measures the interval be-
tween adjacent edges of the demodulated output
signal from the IR amplifier/detector. You can
specify the polarity using the POSED and NEGED
bit in the IRSCR register The measurement is rep-
resented in terms of a count obtained with a
12.5KHz clock and stored in the IRPR register.
Whenever an edge of specified polarity is detect-
ed, the count accumulated since the previously
detected edge is latched into an 8-bit register and
an interrupt request IRQ is generated if the IR-
WDIS bit is reset in the IRSCR register.
Note: Any count less than 255 stored in the latch
register is over-written in case the µP fails to exe-
cute the read before the next edge occurs.
In case an edge is not detected in about 20ms (the
count reaches its maximum value of 255) the
count is latched immediately and the IRQ flag is
set. An overflow flag (not accessable) is also set
internally.
Each time an interrupt is received, it must be ac-
knowleged by writing any value in the IRPR regis-
ter. Otherwise no further interrupts will be generat-
ed.
Warning: The content of the latch cannot be
changed as long as the overflow flag remains set.
To clear the IRQ and internal overflow flags, just
write any value in the IRPR register. As long as the
internal overflow flag is set, no interrupt is generat-
ed.
The IR input signal is preprocessed by a spike fil-
ter. The FLSEL bit of the IRSCR register deter-
mines the width of filtered pulse.
8.8.2 Register Description
IR PULSE REGISTER (IRPR)
R248 - Read only
Register Page: 43
Reset Value: 0000 0000 (00h)
169/268
- IR PREPROCESSOR (IR)
IR7
7
IR6
IR5
IR4
IR3
IR2
IR1
IR
0
0
Bits 7:0 = IR[7:0]: IR pulse width in terms of
number of 12.5KHz clock cycles.
IR/SYNC CONTROL REGISTER (IRSCR)
R250 - Read/Write
Register Page: 43
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved. Forced by hardware to 0.
Bit 5 = Reserved (used for Sync Error Detector).
Refer to the Sync Error Detector chapter.
Bit 4 = IRWDIS: External Interrupt Source.
This bit is set and cleared by software. It selects
the source of the interrupt assigned to the external
interrupt channel. Refer to the Interrupt Chapter.
0: The interrupt request from the IR preprocessor
1: The interrupt from the external interrupt pin is
Bit 3 = FLSEL: Spike filter pulse width selection
This bit is set and cleared by software. It selects
the spike filter width.
0: Filter pulses narrower than 2µs
1: Filter pulses narrower than 160µs
Bit 2:1 = POSED, NEGED Edge selection for the
duration measurement
Bit 0 = Reserved (used for Sync Error Detector).
NEGED POSED
7
0
is forwarded to the CPU
forwarded to the CPU
1
1
0
0
0
1
0
1
0
-
IRWDIS FLSEL POSED NEGED
Positive or negative transition of
IR or when count reaches 255
Negative transition of IR or when
count reaches 255
Positive transition of IR or when
count reaches 255
Only when count reaches 255
Count latch at ...
0
-