ST92196A STMicroelectronics, ST92196A Datasheet - Page 69

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

6.2 REGISTER DESCRIPTION
SKEW CLOCK CONTROL REGISTER (SKCCR)
R254 - Read/ Write
Register Page: 43
Reset value: 0000 0000 (00h)
The HALT mode forces the register to its initializa-
tion state.
Bit 7= SKWEN: Frequency Multiplier Enable bit.
0: FM disabled (reset state), low-power consump-
1: FM is enabled providing clock to the Skew cor-
Bit 6 = SKDIV2: Skew Divide-by-2 Enable bit.
0: Divide-by-2 disabled.
1: Divide-by-2 enabled.
This bit must be kept in reset state.
Bit 5:4 = Reserved. These bits are forced to 0 by
hardware.
Bit 3:0 = SKW: Skew Counter.
These 4 bits program the down-counter inserted in
the feedback loop of the Frequency Multiplier
which generates the internal multiplied frequency
PIXCLK. The PIXCLK value is calculated as fol-
lows :
If FPIXC=0 :
F(PIXCLK)=Crystal frequency * [ (SKW(3:0)+1) ]/2
If FPIXC=1 :
F(PIXCLK)=Crystal frequency * [ (SKW(3:0)+1) ]
Note: To program the FPIXC bit, refer to the de-
scription of the OSDER register in the OSD chap-
ter.
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SKWEN SKDIV2
TIMING AND CLOCK CONTROLLER (TCC)
tion mode.
rector. The SKWEN bit must be set only after
programming the SKW(3-0) bits.
7
6
5
0
4
0
SKW3 SKW2 SKW1 SKW0
3
2
1
0
MAIN CLOCK CONTROL REGISTER (MCCR)
R253 - Read/ Write
Register Page: 43
Reset value: 0000 0000 (00h)
The HALT mode forces the register to its initializa-
tion state.
Bit 7 = FMEN: Frequency Multiplier Enable bit .
0: FM disabled (reset state), low-power consump-
1: FM is enabled, providing clock to the CPU. The
Bit 6= FMSL: Frequency Multiplier Select bit.
This bit controls the choice of the ST9 core internal
frequency between the external crystal frequency
and the Main Clock issued by the frequency multi-
plier.
In order to secure the application, the ST9 core in-
ternal frequency is automatically switched back to
the external crystal frequency if the frequency mul-
tiplier is switched off (FMEN =0) regardless of the
value of the FMSL bit. Care must be taken to reset
the FMSL bit before any frequency multiplier can
restart (FMEN set back to 1).
After reset, the external crystal frequency is al-
ways sent to the ST9 Core.
Bit 5:4 = Reserved. These bits are forced to 0 by
hardware.
Bit 3:0 = FML: FM Counter.
These 4 bits program the down-counter inserted in
the feed-back loop of the Frequency Multiplier
which generates the internal multiplied frequency
Fimf. The Fimf value is calculated as follows :
Fimf = Crystal frequency * [ (FML(3:0) + 1) ] /2
FMEN FMSL
tion mode.
FMEN bit must be set only after programming
the FML(3:0) bits.
7
6
5
0
4
0
FML3 FML2 FML1 FML0
3
2
1
0