ST92196A STMicroelectronics, ST92196A Datasheet - Page 217

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

PWM GENERATOR (Cont’d)
AUTOCLEAR REGISTER (ACR)
R248 - Read/Write
Register Page: 59
Reset Value: 1111 1111 (FFh)
This register behaves exactly as a 9th compare
Register, but its effect is to clear the CRR counter
register, so causing the desired PWM repetition
rate.
The reset condition generates the free running
mode. So, FFh means count by 256.
Bit 7:0 = AC[7:0]: Autoclear Count Value.
When 00 is written to the Compare Register, if the
ACR register = FFh, the PWM output bit is always
set except for the last clock count (255 set and 1
reset; the converse when the output is comple-
mented). If the ACR content is less than FFh, the
PWM output bit is set for a number of clock counts
equal to that content (see Figure 2).
Writing the Compare register constant equal to the
ACR register value causes the output bit to be al-
ways reset (or set if complemented).
Example: If 03h is written to the Compare Regis-
ter, the output bit is reset when the CRR counter
reaches the ACR register value and set when it
reaches the Compare register value (after 4 clock
counts, see
if the output is complemented. The PWM mark/
space ratio will remain constant until changed by
software writing a new value in the ACR register.
COUNTER REGISTER (CRR)
R249 - Read Only
Register Page: 59
Reset Value: 0000 0000 (00h)
This read-only register returns the current counter
value when read.
The 8 bit Counter is initialized to 00h at reset, and
is a free running UP counter.
Bit 7:0 = CR[7:0]: Current Counter Value.
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- PWM GENERATOR
AC7
CR7
7
7
AC6
CR6
Figure
AC5
CR5
97). The action will be reversed
AC4
CR4
CR3
AC3
AC2
CR2
CR1
AC1
CR0
AC0
0
0
PRESCALER
(PCTL)
R250 - Read/Write
Register Page: 59
Reset Value: 0000 1100 (0Ch)
Bit 7:4 = PR[3:0] PWM Prescaler value .
These bits hold the Prescaler preset value. This is
reloaded into the 4-bit prescaler whenever the
prescaler (DOWN Counter) reaches the value 0,
so determining the 8-bit Counter count frequency.
The value 0 corresponds to the maximum counter
frequency which is INTCLK/2. The value Fh corre-
sponds to the maximum frequency divided by 16
(INTCLK/32).
The reset condition initializes the Prescaler to the
Maximum Counter frequency.
Bit 3:2 = Reserved. Forced by hardware to “1”
Bit 1 = CLR: Counter Clear.
This bit when set, allows both to clear the counter,
and to reload the prescaler. The effect is also to
clear the PWM output. It returns “0” if read.
Bit 0 = CE: Counter Enable.
This bit enables the counter and the prescaler
when set to “1”. It stops both when reset without
affecting their current value, allowing the count to
be suspended and then restarted by software “on
fly”.
PR3
PR[3:0]
7
Fh
0
1
2
..
PR2
Divider Factor
PR1
AND
16
1
2
3
..
PR0
CONTROL
1
Frequency
INTCLK/2 (Max.)
INTCLK/4
INTCLK/6
..
INTCLK/32 (Min.)
1
REGISTER
CLR
CE
0