ST92196A STMicroelectronics, ST92196A Datasheet - Page 160

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

8.6 CLOSED CAPTION DATA SLICER (DS)
8.6.1 Introduction
Depending on the ST9 device, one or two Data
Slicers may be available in the MCU (refer the de-
vice feature list and Register map).
Each Data Slicer can extract either
The Data Slicer automatically determines the data
format in the specified line and sets the appropri-
ate flag.
8.6.2 Functional Description
Inputs
CCVIDEO: Composite video signal AC coupled
HSYNC:
VSYNC:
F_4MHz:
Figure 67. Block Diagram
1µF
Closed caption data from a composite video
signal broadcast in the EIA-608 format. Used in
conjunction with the OSD, it allows closed
caption information to be displayed on a TV
screen.
Gemstar format data transmitted on one or more
horizontal lines in the vertical blanking interval.
In this format, one line contains 4 bytes of data.
Vref (Sync)
Vref (Black)
CCVIDEO
through a 1µF capacitor.
Horizontal deflection pulse.
Vertical deflection pulse.
4 MHz clock from frequency
multiplier.
Vslice
-
+
-
+
-
+
Vref
CSYNC
UP/DOWN
COUNTER
CLAMP
PROCESSOR
GENERATOR
Outputs
IRQ:
As shown in
incoming composite video as an AC coupled sig-
nal through a 1µF capacitor to the CCVIDEO pin.
The OSD synchronization signals and a 4 MHz
crystal derived clock are used in the data slicer
signal extraction logic.
Data extraction can be programmed for a selecta-
ble line in either field for a video signal of ampli-
tude of 2V +/-3dB. The slicing level for data is con-
trolled automatically by hardware.
The output signal DSOUT is high when the input
signal exceeds the level of the reference voltage
Vslice, and low when it is less than Vslice.
The clamp is disabled from the time of detection of
vertical sync in CCVIDEO (a sync pulse wider than
12µs) up to line 28.
Note: For good slicing results, it is advised to set
VDDA >= 5.3V. Remember also that VDDA < VDD
+ 0.3V.
CLOCK
- CLOSED CAPTION DATA SLICER (DS)
DATA
Figure
Conditional negative edge interrupt
request, connected to a CPU
interrupt channel (See Interrupts
Chapter).
REGISTERS
DATA
67, the Data Slicer accepts the
(from Frequency Multiplier)
4 MHz
Interrupt
REGISTER
STATUS
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