ST92196A STMicroelectronics, ST92196A Datasheet - Page 64

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

5 RESET AND CLOCK CONTROL UNIT (RCCU)
5.1 INTRODUCTION
The Reset and Clock Control Unit (RCCU) com-
prises two distinct sections:
– the Clock Control Unit, which generates and
– the Reset/Stop Manager, which detects and
5.2 CLOCK CONTROL REGISTERS
MODE REGISTER (MODER)
R235 - Read/Write
System Register
Reset Value: 1110 0000 (E0h)
*Note: This register contains bits which relate to
other functions; these are described in the chapter
dealing with Device Architecture. Only those bits
relating to Clock functions are described here.
Bit 5 = DIV2: OSCIN Divided by 2 .
This bit controls the divide by 2 circuit which oper-
ates on the OSCIN Clock.
0: No division of the OSCIN Clock
1: OSCIN clock is internally divided by 2
Bit 4:2 = PRS[2:0]: Clock Prescaling .
These bits define the prescaler value used to pres-
cale CPUCLK from INTCLK. When these three
bits are reset, the CPUCLK is not prescaled, and is
equal to INTCLK; in all other cases, the internal
clock is prescaled by the value of these three bits
plus one.
manages the internal clock signals.
flags Hardware, Software and Watchdog gener-
ated resets.
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DIV2
PRS2
PRS1
PRS0
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0
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RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTER (CLKCTL)
R240 - Read Write
Register Page: 55
Reset Value: 0000 0000 (00h)
Bit 7:4 = Reserved.
Must be kept reset for normal operation.
Bit 3 = SRESEN: Software Reset Enable.
0: The HALT instruction turns off the quartz, the
1: A Reset is generated when HALT is executed
Bit 2:0 = Reserved.
Must be kept reset for normal operation.
CLOCK FLAG REGISTER (CLK_FLAG)
R242 - Read/Write
Register Page: 55
Reset Value: 0100 1000 after a Watchdog Reset
Reset Value: 0010 1000 after a Software Reset
Reset Value: 0000 1000 after a Power-On Reset
WARNING: If this register is accessed with a logi-
cal instruction, such as AND or OR, some bits may
not be set as expected.
Bit 7 = Reserved.
Must be kept reset for normal operation.
Bit 6 = WDGRES: Watchdog reset flag.
This bit is read only.
0: No Watchdog reset occurred
1: Watchdog reset occurred
Bit 5 = SOFTRES: Software Reset Flag.
This bit is read only.
0: No software reset occurred
1: Software reset occurred (HALT instruction)
Bit 4:0 = Reserved.
Must be kept reset for normal operation.
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PLL and the CCU
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7
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WDG
RES
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SOFT
RES
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SRE-
SEN
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