ST92196A STMicroelectronics, ST92196A Datasheet - Page 75

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

7.5 ALTERNATE FUNCTION ARCHITECTURE
Each I/O pin may be connected to three different
types of internal signal:
– Data bus Input/Output
– Alternate Function Input
– Alternate Function Output
7.5.1 Pin Declared as I/O
A pin declared as I/O, is connected to the I/O buff-
er. This pin may be an Input, an Output, or a bidi-
rectional I/O, depending on the value stored in
(PxC2, PxC1 and PxC0).
7.5.2 Pin Declared as an Alternate Function
Input
A single pin may be directly connected to several
Alternate Function inputs. In this case, the user
must select the required input mode (with the
PxC2, PxC1, PxC0 bits) and enable the selected
Alternate Function in the Control Register of the
peripheral. No specific port configuration is re-
quired to enable an Alternate Function input, since
the input buffer is directly connected to each alter-
nate function module on the shared pin. As more
than one module can use the same input, it is up to
the user software to enable the required module
as necessary. Parallel I/Os remain operational
even when using an Alternate Function input. The
exception to this is when an I/O port bit is perma-
nently assigned by hardware as an A/D bit. In this
case , after software programming of the bit in AF-
OD-TTL, the Alternate function output is forced to
logic level 1. The analog voltage level on the cor-
responding pin is directly input to the A/D (See
ure
Figure 40. A/D Input Configuration
75/268
- ALTERNATE FUNCTION ARCHITECTURE
TRISTATE
40).
OUTPUT MASTER LATCH
OUTPUT SLAVE LATCH
INTERNAL DATA BUS
I/O PIN
INPUT LATCH
GND
BUFFER
TOWARDS
A/D CONVERTER
INPUT
Fig-
7.5.3 Pin Declared as an Alternate Function
Output
The user must select the AF OUT configuration
using the PxC2, PxC1, PxC0 bits. Several Alter-
nate Function outputs may drive a common pin. In
such case, the Alternate Function output signals
are logically ANDed before driving the common
pin. The user must therefore enable the required
Alternate Function Output by software.
WARNING: When a pin is connected both to an al-
ternate function output and to an alternate function
input, it should be noted that the output signal will
always be present on the alternate function input.
7.6 I/O STATUS AFTER WFI, HALT AND RESET
The status of the I/O ports during the Wait For In-
terrupt, Halt and Reset operational modes is
shown in the following table. The External Memory
Interface ports are shown separately. If only the in-
ternal memory is being used and the ports are act-
ing as I/O, the status is the same as shown for the
other I/O ports.
RESET
Mode
HALT
WFI
address (de-
High Imped-
ance or next
High Imped-
memory op-
Alternate function push-
pull (ROMless device)
eration per-
pending on
formed on
Ext. Mem - I/O Ports
the last
Port)
ance
P0
Address
Address
P1, P2,
P6, P9
Next
Next
Not Affected (clock
outputs running)
Not Affected (clock
outputs stopped)
Bidirectional Weak
Pull-up (High im-
pedance when disa-
bled in hardware).
I/O Ports