ST92196A STMicroelectronics, ST92196A Datasheet - Page 176

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

I
FREQUENCY REGISTER (I2CFQR)
R241 - Read/Write
Register Page: 44
Reset Value: 0000 0000(00h)
Bits 7:6 = BUS_S[1:0] I
These bits connect the I
four possible buses as described in
Table 35. I
Bit 5 = FMEN Fast Mode Enable bit
This bit enables or disables the fast mode for the
SCL bus frequency.
0: Standard Mode (up to 100 kHz).
1: Fast Mode (over 100 kHz)
Bit 4 = PP_DRV Push-Pull Drive mode bit
This bit determines if the master drives the SCL/
SDA buses in push-pull mode or in normal mode.
This allows the master to send data to the slave at
a faster speed.
0: The push-pull drive mode is disabled
1: The push-pull drive mode is enabled. All “nor-
Note: The master automatically switches tempo-
rarily to normal bus driving mode with active pull-
up disabled and SCL frequency reduced by factor
of 2 when receiving acknowledges or data from
the addressed slave.
Bit 3:0 = Q[3:0] SCL clock frequency bits
These bits select the SCL clock frequency when
the interface works in master mode. In slave trans-
mitter mode, they can be used to adjust the setting
up time between the first data byte and the clock.
Refer to
BUS_S0 BUS_S1 FMEN PP_DRV
2
C BUS INTERFACE (Cont’d)
7
mal” bus frequencies are doubled with the only
exception that the push-pull drive mode is auto-
matically disabled when Q[3:0]=1110 or
Q[3:0]=1111 to yield an SCL frequency of 500
kHz or 800 kHz. Refer to Q[3:0] bit description.
BUS_S1
0
0
1
1
Table
2
C bus selection
36.
BUS_S0
0
1
0
1
2
2
C BUS Selection bits
C interface to one of the
Q3
Selected Bus
Q2
SCL1/SDA1
SCL2/SDA2
SCL3/SDA3
SCL4/SDA4
Table
Q1
35.
Q0
0
- FOUR-CHANNEL I
In push-pull mode, the frequency values present-
ed in the following table correspond to an approxi-
mate frequency assuming that :
– the first data bit is transferred at a lower frequen-
– the acknowledge bit is transferred at the slave
– other data bits are transferred with a real period
Using the spike filter will add an internal delay act-
ing as a period increase by 250-ns steps.
Table 36. SCL Clock Frequency Selection
*
specification
Notes:
– The maximum allowed frequency depends on
– All frequency values depend on the bus line load
– All above values are obtained with loads corre-
– Any higher rise time (especially in standard
Q[3:0]
These values are not covered by the Philips I
cy (clock stretching capability),
speed without push-pull mode,
250 ns shorter than the values indicated in this
table.
the state of the FMEN control bit (If PP_DRV=0,
standard mode: 100 KHz; fast mode: 666.6 kHz)
(except push-pull mode).
sponding to a rise time from 0 to 250 ns.
mode) will increase the period of the bus line fre-
quency by 250-ns steps.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SCL max Frequency
PP_DRV = 0
SCL BUS FREQUENCY (in kHz)
444.44
666.67
102.56
129.03
173.91
210.53
266.67
400.00
444.44
20.10
30.53
40.40
50.63
63.49
72.73
85.11
2
C BUS INTERFACE (I2C)
*
*
SCL Frequency (kHz)
(period: +0/-250ns
PP_DRV = 1
102.56
129.03
148.15
173.91
210.53
266.67
363.64
444.44
444.44
571.43
666.67
666.67
666.67
40.40
61.54
81.63
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2
C