mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 18

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Table 11:
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
128mb_mobile_sdram_y35m__2.fm - Rev. B 6/08 EN
Parameter
WRITE command to input data delay
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
CKE to clock enable or power-down exit mode
Last data-in to PRECHARGE command
Data-out High-Z from PRECHARGE command
AC Functional Characteristics (continued)
Notes 1–5 apply to all parameters
Notes:
10. For auto precharge mode, the precharge timing budget (
11. CLK must be toggled a minimum of two times during this period.
12. Required clocks are specified by JEDEC functionality and are not dependent on any timing
13. Timing is specified by
14. Timing is specified by
15. Timing is specified by
16. Based on
1. A full initialization sequence is required before proper device operation is ensured.
2. The minimum specifications are used only to indicate cycle time at which proper operation
3. In addition to meeting the transition rate specification, the clock and CKE must transit
4. Outputs measured for 1.8V at 0.9V with equivalent load:
5. AC timing tests have V
6. The clock frequency must remain constant (stable clock is defined as a signal cycling within
7.
8. The 128Mb Mobile SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (
9. AC characteristics assume
over the full temperature range (–40°C ≤ T
between V
Test loads with full DQ driver strength. Performance will vary with actual system DQ bus
capacitive loading, termination, and programmed drive strength.
input transition time is longer than
and V
timing constraints specified for the clock ball) during access or precharge states (READ,
WRITE, including
rate.
t
erence to V
ing a distributed AUTO REFRESH command every 15.6µs meets the refresh requirement and
ensures that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate (
-6, after the first clock delay and after the last WRITE is executed.
parameter.
rate.
Q
HZ defines the time at which the output achieves the open circuit condition, it is not a ref-
IH
(MIN) and no longer at the V
t
CK (MIN), CL = 3.
IH
OH
and V
or V
20pF
t
WR, and PRECHARGE commands). CKE may be used to reduce the data
OL
IL
CL =
CL =
. The last valid data element will meet
(or between V
t
t
t
3
2
IL
CKS. Clock(s) specified as a reference only at minimum cycle rate.
WR plus
WR.
and Vih with timing referenced to V
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
t
T = 1ns.
t
t
t
t
t
Symbol
DWD
MRD
PED
RDL
ROH
18
t
RP. Clock(s) specified as a reference only at minimum cycle
IL
t
T (MAX), then the timing is referenced at V
and V
IH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
/2 crossover point.
A
-75
IH
0
2
1
2
3
2
≤ +85°C industrial temperature) is ensured.
t
) in a monotonic manner.
RFC), one time for every 64ms.
t
RP) begins at 7.5ns for -75, 9ns for
Electrical Specifications
-8
t
0
2
1
2
3
2
OH before going High-Z.
IH
/2 = crossover point. If the
©2008 Micron Technology, Inc. All rights reserved.
Unit
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK
t
REF). Provid-
Preliminary
IL
(MAX)
Notes
15, 16
12
13
12