mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 35

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Figure 13:
Burst Length (BL)
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
Mn+2 Mn+1
0
0
1
1
Mode Register Definition
0
1
0
1
Mn+2
n+2 n+1
0
Mode Register Definition
Base mode register
Reserved
Extended mode register
Reserved
BA1
M9
0
1
Read and write accesses to the SDRAM are burst oriented, with the BL being program-
mable, as shown in Figure 13 on page 35. The BL determines the maximum number of
column locations that can be accessed for a given READ or WRITE command. Burst
length of 1, 2, 4, 8, or continuous locations are available for both the sequential and the
interleaved burst types, and a continuous page burst is available for the sequential type.
The continuous page burst is used in conjunction with the BURST TERMINATE
command to generate arbitrary BLs.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the BL is effec-
tively selected. All accesses for that burst take place within this block, meaning that the
burst wraps within the block if a boundary is reached. The block is uniquely selected by
Mn+1
0
BA0
Programmed burst length
M8
Single location access
0
–
Write Burst Mode
An
Mn
n
Reserved*
M7
0
–
...
...
...
Normal operation
All other states reserved
Operating Mode
10
A10
M10
WB
M6
0
0
0
0
1
1
1
1
A9
M9
9
Op mode
M5
0
0
1
1
0
0
1
1
M8
A8
8
M4
0
1
0
1
0
1
0
1
A7
M7
7
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
CAS latency
35
M6
A6
6
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M5
5
A5
2
3
4
A4
M4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BT
M3
A3
3
M2
Burst length
0
0
0
0
1
1
1
1
A2
M2
2
M1
0
0
1
1
0
0
1
1
A1
M1
1
M0
M3
0
1
0
1
0
1
0
1
0
1
A0
M0
0
*Should be
programmed
to “0” to ensure
compatibility
with future
devices.
Continuous
Reserved
Reserved
Reserved
M3 = 0
Interleaved
Burst Type
Sequential
1
2
4
8
Address bus
Mode
register (Mx)
Burst Length
©2008 Micron Technology, Inc. All rights reserved.
Register Definition
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
Preliminary