mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 38

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Figure 15:
Temperature-Compensated Self Refresh (TCSR)
Partial-Array Self Refresh (PASR)
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
En + 2
0
0
1
1
En + 1
Extended Mode Register
0
1
0
1
En
0
–
Mode Register Definition
Status register
Extended mode register
Reserved
...
Notes:
0
–
E10
0
–
E9
0
1. All banks (banks 0, 1, 2, and 3)
2. Two banks (banks 0 and 1; BA1= 0)
3. One bank (bank 0; BA1 = BA0 = 0)
–
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
The EMR must be programmed with E7–En set to “0.” It must be loaded when all banks
are idle and no bursts are in progress, and the controller must wait the specified time
before initiating any subsequent operation. Violating either of these requirements
results in unspecified operation. After the values are entered, the EMR settings are
retained even after exiting deep power-down mode.
Mobile SDRAMs include a temperature sensor that is implemented for automatic
control of the self refresh oscillator on the device. Therefore, it is recommended that the
TCSR control bits in the EMR not be programmed or used. Programming the TCSR bits
has no effect on the device. The self refresh oscillator will continue refresh at the optimal
factory programmed rate for the device temperature.
For further power savings during self refresh, the PASR feature enables the controller to
select the amount of memory that is refreshed during self refresh. The following refresh
options are available:
n+2
1
BA1
E8
0
–
n+1
0
BA0
E7–E0
Valid
–
An
n
...
Normal Operation
All other states reserved
Operation
...
10
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E7
0
0
0
0
1
1
1
1
E6
0
0
1
1
0
0
1
1
9
E5
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
0
1
0
1
0
1
0
1
8
38
7
DS
6
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
E2
0
0
0
0
1
1
1
1
TCSR
4
E1
0
0
1
1
0
0
1
1
1
3
E0
0
1
0
1
0
1
0
1
2
PASR
Partial-Array Self Refresh Coverage
Full array
Half array
Quarter array
Reserved
Reserved
One-eighth array
One-sixteenth array
Reserved
1
0
©2008 Micron Technology, Inc. All rights reserved.
Register Definition
Address bus
Extended mode
register (Ex)
Preliminary