mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 61

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Figure 40:
WRITE with Auto Precharge
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
Command
BA0, BA1
Address
DQM
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
T0
Bank
Row
Row
Single READ – Without Auto Precharge
t CMH
t AH
t AH
t AH
t CKH
t RCD
t RAS
t RC
Notes:
t CK
T1
NOP
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRECHARGE
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (see Figure 41).
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered one clock prior to a WRITE to
bank m (see Figure 42).
Disable auto precharge
t CMS
t CL
Column m
t
T2
Bank
READ
WR is met, where
t CH
t CMH
CL = 2
T3
NOP
t LZ
t AC
t
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
WR begins when the WRITE to bank m is registered. The last
61
T4
NOP
D
OUT
t OH
t HZ
m
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t
Single bank
WR is met, where
All banks
PRECHARGE
Bank(s)
T5
T6
t RP
NOP
t
WR begins when the READ to
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ACTIVE
Row
Bank
Row
T7
Timing Diagrams
T8
NOP
Preliminary
Don’t Care
Undefined