mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 42

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Figure 18:
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
Random READ Accesses
Notes:
1. Each READ command can be to any bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there is a possibility that the device driving the input data will go Low-Z before
the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 19 on page 43 and
Figure 20 on page 44. The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-
out from the READ. After the WRITE command is registered, the DQs will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be
invalid.
Command
Command
Address
Address
CLK
CLK
DQ
DQ
T0
T0
READ
Bank,
READ
Bank,
Col n
Col n
CL = 2
T1
T1
Bank,
READ
READ
Bank,
Col a
Col a
CL = 3
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
42
T2
T2
Bank,
Bank,
READ
READ
Col x
Col x
D
OUT
n
T3
T3
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Col m
Col m
READ
Bank,
READ
Bank,
D
D
OUT
OUT
a
n
T4
T4
NOP
NOP
D
D
OUT
OUT
x
a
T5
T5
NOP
NOP
D
D
OUT
m
OUT
x
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Don’t Care
T6
NOP
Timing Diagrams
D
OUT
m
Preliminary