mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 68

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Figure 48:
Power-Down
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
Command
BA0, BA1
Address
DQM
CKE
A10
CLK
DQ
High-Z
Precharge all
t CKS
active banks
t CMS
t
Self Refresh Mode
AS
PRECHARGE
Single bank
All banks
Bank(s)
T0
Notes:
t CKH
t CMH
t
AH
t CK
1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock ball) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued
according to the distributed refresh rate (
REFRESH and AUTO REFRESH utilize the row refresh counter.
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
t RP
required.
T1
NOP
t CH
Enter self refresh mode
t CKS
t CL
REFRESH
CLK stable prior to exiting
AUTO
T2
self refresh mode
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
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(Restart refresh time base)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Exit self refresh mode
t
REF/refresh row count) as both SELF
Tn + 1
t XSR
NOP
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To + 1
t
XSR because time is
©2008 Micron Technology, Inc. All rights reserved.
Timing Diagrams
To + 2
REFRESH
AUTO
Don’t Care
Preliminary